Patch "intel_idle: Update support for Silvermont Core in Baytrail SOC" has been added to the 4.0-stable tree

This is a note to let you know that I've just added the patch titled

intel_idle: Update support for Silvermont Core in Baytrail SOC

to the 4.0-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
intel_idle-update-support-for-silvermont-core-in-baytrail-soc.patch
and it can be found in the queue-4.0 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree, please let <[email protected]> know about it.

From: Len Brown <[email protected]>
Date: Tue, 24 Mar 2015 23:23:20 -0400
Subject: intel_idle: Update support for Silvermont Core in Baytrail SOC

From: Len Brown <[email protected]>

commit d7ef76717322c8e2df7d4360b33faa9466cb1a0d upstream.

On some Silvermont-Core/Baytrail-SOC systems,
C1E latency is higher than original specifications. Although C1E is still enumerated in CPUID.MWAIT.EDX, we delete the state from intel_idle to avoid latency impact.

Under some conditions, the latency of the C6N-BYT and C6S-BYT states may exceed the specified values of 40 and 140 usec, respectively. Increase those values to 300 and 500 usec; to assure
that the hardware does not violate constraints that may be set by the Linux PM_QOS sub-system.

Also increase the C7-BYT target residency to 4.0 ms from 1.5 ms.

---
 drivers/idle/intel_idle.c |   14 +++-----------
 1 file changed, 3 insertions(+), 11 deletions(-)

@@ -218,18 +218,10 @@ static struct cpuidle_state byt_cstates[
 		.enter = &intel_idle,
 		.enter_freeze = intel_idle_freeze, },
 	{
-		.name = "C1E-BYT",
-		.desc = "MWAIT 0x01",
-		.flags = MWAIT2flg(0x01),
-		.exit_latency = 15,
-		.target_residency = 30,
-		.enter = &intel_idle,
-		.enter_freeze = intel_idle_freeze, },
-	{
 		.name = "C6N-BYT",
 		.desc = "MWAIT 0x58",
 		.flags = MWAIT2flg(0x58) | CPUIDLE_FLAG_TLB_FLUSHED,
-		.exit_latency = 40,
+		.exit_latency = 300,
 		.target_residency = 275,
 		.enter = &intel_idle,
 		.enter_freeze = intel_idle_freeze, },

@@ -237,7 +229,7 @@ static struct cpuidle_state byt_cstates[
 		.name = "C6S-BYT",
 		.desc = "MWAIT 0x52",
 		.flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TLB_FLUSHED,
-		.exit_latency = 140,
+		.exit_latency = 500,
 		.target_residency = 560,
 		.enter = &intel_idle,
 		.enter_freeze = intel_idle_freeze, },

@@ -246,7 +238,7 @@ static struct cpuidle_state byt_cstates[
 		.desc = "MWAIT 0x60",
 		.flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
 		.exit_latency = 1200,
-		.target_residency = 1500,
+		.target_residency = 4000,
 		.enter = &intel_idle,
 		.enter_freeze = intel_idle_freeze, },
 	{

Patches currently in stable-queue which might be from [email protected] are

queue-4.0/intel_idle-update-support-for-silvermont-core-in-baytrail-soc.patch queue-4.0/sched-idle-x86-optimize-unnecessary-mwait_idle-resched-ipis.patch queue-4.0/sched-idle-x86-restore-mwait_idle-to-fix-boot-hangs-to-improve-power-savings-and-to-improve-performance.patch