i2c, mxc: rework i2c base address names for different SoCs

PATCH Superseded Heiko Schocher 1 participant 1 message May 13, 2015

Subsystems (3)

Arm (32-bit) Arm i.MX and Layerscape I2C

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Heiko Schocher

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2015-05-13 05:53 UTC #0 lore raw

PATCH 1/1 i2c, mxc: rework i2c base address names for different SoCs

rework and unify i2c address names for different SoCs, which use the mxc_i2c driver.

Signed-off-by Heiko Schocher <[email protected]>

---

 arch/arm/include/asm/arch-imx/imx-regs.h   |  2 +-
 arch/arm/include/asm/arch-mx25/imx-regs.h  |  6 ++---
 arch/arm/include/asm/arch-mx27/imx-regs.h  |  4 +--
 arch/arm/include/asm/arch-vf610/imx-regs.h |  2 +-
 drivers/i2c/mxc_i2c.c                      | 43 +++++++++++++++---------------
 5 files changed, 28 insertions(+), 29 deletions(-)

arch/arm/include/asm/arch-imx/imx-regs.h +1 -1

index 4de0779..93e3369 100644
@@ -42,7 +42,7 @@
 #define IMX_MMC_BASE               (0x14000 + IMX_IO_BASE)
 #define IMX_ASP_BASE               (0x15000 + IMX_IO_BASE)
 #define IMX_BTA_BASE               (0x16000 + IMX_IO_BASE)
-#define IMX_I2C_BASE               (0x17000 + IMX_IO_BASE)
+#define I2C1_BASE_ADDR             (0x17000 + IMX_IO_BASE)
 #define IMX_SSI_BASE               (0x18000 + IMX_IO_BASE)
 #define IMX_SPI2_BASE              (0x19000 + IMX_IO_BASE)
 #define IMX_MSHC_BASE              (0x1A000 + IMX_IO_BASE)

arch/arm/include/asm/arch-mx25/imx-regs.h +3 -3

index 3dffa4a..78c4e9b 100644
@@ -293,13 +293,13 @@ struct cspi_regs {
 #define IMX_ETB_SLOT4_BASE	(0x43F0C000)
 #define IMX_ETB_SLOT5_BASE	(0x43F10000)
 #define IMX_ECT_CTIO_BASE	(0x43F18000)
-#define IMX_I2C_BASE		(0x43F80000)
-#define IMX_I2C3_BASE		(0x43F84000)
+#define I2C1_BASE_ADDR		(0x43F80000)
+#define I2C3_BASE_ADDR		(0x43F84000)
 #define IMX_CAN1_BASE		(0x43F88000)
 #define IMX_CAN2_BASE		(0x43F8C000)
 #define UART1_BASE		(0x43F90000)
 #define UART2_BASE		(0x43F94000)
-#define IMX_I2C2_BASE		(0x43F98000)
+#define I2C2_BASE_ADDR		(0x43F98000)
 #define IMX_OWIRE_BASE		(0x43F9C000)
 #define IMX_CSPI1_BASE		(0x43FA4000)
 #define IMX_KPP_BASE		(0x43FA8000)

arch/arm/include/asm/arch-mx27/imx-regs.h +2 -2

index 92c847e..82cee19 100644
@@ -194,13 +194,13 @@ struct fuse_bank0_regs {
 #define UART2_BASE		(0x0b000 + IMX_IO_BASE)
 #define UART3_BASE		(0x0c000 + IMX_IO_BASE)
 #define UART4_BASE		(0x0d000 + IMX_IO_BASE)
-#define IMX_I2C1_BASE		(0x12000 + IMX_IO_BASE)
+#define I2C1_BASE_ADDR		(0x12000 + IMX_IO_BASE)
 #define IMX_GPIO_BASE		(0x15000 + IMX_IO_BASE)
 #define IMX_TIM4_BASE		(0x19000 + IMX_IO_BASE)
 #define IMX_TIM5_BASE		(0x1a000 + IMX_IO_BASE)
 #define IMX_UART5_BASE		(0x1b000 + IMX_IO_BASE)
 #define IMX_UART6_BASE		(0x1c000 + IMX_IO_BASE)
-#define IMX_I2C2_BASE		(0x1D000 + IMX_IO_BASE)
+#define I2C2_BASE_ADDR		(0x1D000 + IMX_IO_BASE)
 #define IMX_TIM6_BASE		(0x1f000 + IMX_IO_BASE)
 #define IMX_AIPI2_BASE		(0x20000 + IMX_IO_BASE)
 #define IMX_PLL_BASE		(0x27000 + IMX_IO_BASE)

arch/arm/include/asm/arch-vf610/imx-regs.h +1 -1

index a7d765a..2021981 100644
@@ -74,7 +74,7 @@
 #define ESAI_BASE_ADDR		(AIPS0_BASE_ADDR + 0x00062000)
 #define ESAI_FIFO_BASE_ADDR	(AIPS0_BASE_ADDR + 0x00063000)
 #define WDOG_BASE_ADDR		(AIPS0_BASE_ADDR + 0x00065000)
-#define I2C0_BASE_ADDR		(AIPS0_BASE_ADDR + 0x00066000)
+#define I2C1_BASE_ADDR		(AIPS0_BASE_ADDR + 0x00066000)
 #define WKUP_BASE_ADDR		(AIPS0_BASE_ADDR + 0x0006A000)
 #define CCM_BASE_ADDR		(AIPS0_BASE_ADDR + 0x0006B000)
 #define GPC_BASE_ADDR		(AIPS0_BASE_ADDR + 0x0006C000)

drivers/i2c/mxc_i2c.c +21 ~~-22~~

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