Skip to contentSkip to conversation

dm: cpu: Test against cpu_ops->get_info in cpu_get_info()

PATCH New Bin Meng 2 participants 13 messages Jun 12, 2015 1 message not in the archive x86

lore
Share & tools
lore

A message that is not in the archive (sent off-list or not yet received): [email protected]

Bin Meng

author
#1 lore raw

PATCH v2 2/9 dm: cpu: Test against cpu_ops->get_info in cpu_get_info()

In cpu_get_info() it wrongly tests against cpu_ops->get_desc to see if it is NULL. It should test against cpu_ops->get_info.

Signed-off-by Bin Meng <[email protected]>

---

Changes in v2: None

 drivers/cpu/cpu-uclass.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/cpu/cpu-uclass.c +1 -1
index aa0267c..d6be9d4 100644
@@ -26,7 +26,7 @@ int cpu_get_info(struct udevice *dev, struct cpu_info *info)
 {
 	struct cpu_ops *ops = cpu_get_ops(dev);
 
-	if (!ops->get_desc)
+	if (!ops->get_info)
 		return -ENOSYS;
 
 	return ops->get_info(dev, info);
Signature · 1 line
1.8.2.1
#2 lore raw

PATCH v2 2/9 dm: cpu: Test against cpu_ops->get_info in cpu_get_info()

Hi Bin,

Quoted 10 lines · Bin Meng

In cpu_get_info() it wrongly tests against cpu_ops->get_desc to see if it is NULL. It should test against cpu_ops->get_info.

Signed-off-by Bin Meng <[email protected]>

---

Changes in v2: None

 drivers/cpu/cpu-uclass.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

I have the same commit locally - I thought I sent it but obviously not.

Acked-by Simon Glass <[email protected]>

Regards,
Simon

#3 lore raw

PATCH v2 2/9 dm: cpu: Test against cpu_ops->get_info in cpu_get_info()

Quoted 9 lines · Simon Glass

Hi Bin,

Quoted 6 lines · Bin Meng

In cpu_get_info() it wrongly tests against cpu_ops->get_desc to see if it is NULL. It should test against cpu_ops->get_info.

Signed-off-by Bin Meng <[email protected]>

---

Quoted 8 lines
Quoted 4 lines

Changes in v2: None

 drivers/cpu/cpu-uclass.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

I have the same commit locally - I thought I sent it but obviously not.

Acked-by Simon Glass <[email protected]>

Applied to u-boot-x86.

author
#4 lore raw

PATCH v2 3/9 x86: dm: Clean up cpu drivers

In reply to a message not in the archive

This commit does the following to clean up x86 cpu dm drivers:
- Move cpu_x86 driver codes from arch/x86/cpu/cpu.c to a dedicated file arch/x86/cpu/cpu_x86.c
- Rename x86_cpu_get_desc() to cpu_x86_get_desc() to keep consistent naming with other dm drivers
- Add a new cpu_x86_bind() in the cpu_x86 driver which does exactly the same as the one in the intel baytrail cpu driver
- Update intel baytrail cpu driver to use cpu_x86_get_desc() and cpu_x86_bind()

Signed-off-by Bin Meng <[email protected]>
Acked-by Simon Glass <[email protected]>

---

Changes in v2: None

 arch/x86/cpu/Makefile          |  2 +-
 arch/x86/cpu/baytrail/cpu.c    | 15 +++----------
 arch/x86/cpu/cpu.c             | 28 ------------------------
 arch/x86/cpu/cpu_x86.c         | 48 ++++++++++++++++++++++++++++++++++++++++++
 arch/x86/include/asm/cpu.h     | 14 ------------
 arch/x86/include/asm/cpu_x86.h | 34 ++++++++++++++++++++++++++++++
 6 files changed, 86 insertions(+), 55 deletions(-)
 create mode 100644 arch/x86/cpu/cpu_x86.c
 create mode 100644 arch/x86/include/asm/cpu_x86.h
arch/x86/cpu/Makefile +1 -1
index 7ff05e6..48197fb 100644
@@ -10,7 +10,7 @@
 
 extra-y	= start.o
 obj-$(CONFIG_X86_RESET_VECTOR) += resetvec.o start16.o
-obj-y	+= interrupts.o cpu.o call64.o
+obj-y	+= interrupts.o cpu.o cpu_x86.o call64.o
 
 obj-$(CONFIG_INTEL_BAYTRAIL) += baytrail/
 obj-$(CONFIG_SYS_COREBOOT) += coreboot/
arch/x86/cpu/baytrail/cpu.c +3 -12
index 1d48206..05156a5 100644
@@ -10,6 +10,7 @@
 #include <cpu.h>
 #include <dm.h>
 #include <asm/cpu.h>
+#include <asm/cpu_x86.h>
 #include <asm/lapic.h>
 #include <asm/mp.h>
 #include <asm/msr.h>

@@ -175,18 +176,8 @@ static int baytrail_get_info(struct udevice *dev, struct cpu_info *info)
 	return 0;
 }
 
-static int cpu_x86_baytrail_bind(struct udevice *dev)
-{
-	struct cpu_platdata *plat = dev_get_parent_platdata(dev);
-
-	plat->cpu_id = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
-				      "intel,apic-id", -1);
-
-	return 0;
-}
-
 static const struct cpu_ops cpu_x86_baytrail_ops = {
-	.get_desc	= x86_cpu_get_desc,
+	.get_desc	= cpu_x86_get_desc,
 	.get_info	= baytrail_get_info,
 };
 

@@ -199,7 +190,7 @@ U_BOOT_DRIVER(cpu_x86_baytrail_drv) = {
 	.name		= "cpu_x86_baytrail",
 	.id		= UCLASS_CPU,
 	.of_match	= cpu_x86_baytrail_ids,
-	.bind		= cpu_x86_baytrail_bind,
+	.bind		= cpu_x86_bind,
 	.probe		= cpu_x86_baytrail_probe,
 	.ops		= &cpu_x86_baytrail_ops,
 };
arch/x86/cpu/cpu.c +0 -28
index bb4a110..ffb6e43 100644
@@ -21,8 +21,6 @@
 
 #include <common.h>
 #include <command.h>
-#include <cpu.h>
-#include <dm.h>
 #include <errno.h>
 #include <malloc.h>
 #include <asm/control_regs.h>

@@ -520,16 +518,6 @@ char *cpu_get_name(char *name)
 	return ptr;
 }
 
-int x86_cpu_get_desc(struct udevice *dev, char *buf, int size)
-{
-	if (size < CPU_MAX_NAME_LEN)
-		return -ENOSPC;
-
-	cpu_get_name(buf);
-
-	return 0;
-}
-
 int default_print_cpuinfo(void)
 {
 	printf("CPU: %s, vendor %s, device %xh\n",

@@ -622,19 +610,3 @@ int cpu_init_r(void)
 {
 	return x86_init_cpus();
 }
-
-static const struct cpu_ops cpu_x86_ops = {
-	.get_desc	= x86_cpu_get_desc,
-};
-
-static const struct udevice_id cpu_x86_ids[] = {
-	{ .compatible = "cpu-x86" },
-	{ }
-};
-
-U_BOOT_DRIVER(cpu_x86_drv) = {
-	.name		= "cpu_x86",
-	.id		= UCLASS_CPU,
-	.of_match	= cpu_x86_ids,
-	.ops		= &cpu_x86_ops,
-};
arch/x86/cpu/cpu_x86.c new file +48 -0

48 lines not on this page · raw message

arch/x86/include/asm/cpu.h +0 -14
index ebc74ad..08284ee 100644
@@ -197,20 +197,6 @@ const char *cpu_vendor_name(int vendor);
 char *cpu_get_name(char *name);
 
 /**
- *
-* x86_cpu_get_desc() - Get a description string for an x86 CPU
-*
-* This uses cpu_get_name() and is suitable to use as the get_desc() method for
-* the CPU uclass.
-*
-* @dev:		Device to check (UCLASS_CPU)
-* @buf:		Buffer to place string
-* @size:	Size of string space
-* @return 0 if OK, -ENOSPC if buffer is too small, other -ve on error
-*/
-int x86_cpu_get_desc(struct udevice *dev, char *buf, int size);
-
-/**
  * cpu_call64() - Jump to a 64-bit Linux kernel (internal function)
  *
  * The kernel is uncompressed and the 64-bit entry point is expected to be
arch/x86/include/asm/cpu_x86.h new file +34 -0
new file mode 100644
index 0000000..1940480
@@ -0,0 +1,34 @@
+/*
+ * Copyright (C) 2015, Bin Meng <[email protected]>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _ASM_CPU_X86_H
+#define _ASM_CPU_X86_H
+
+/**
+ * cpu_x86_bind() - Bind an x86 CPU with the driver
+ *
+ * This updates cpu device's platform data with information from device tree,
+ * like the processor local apic id.
+ *
+ * @dev:	Device to check (UCLASS_CPU)
+ * @return	0 always
+ */
+int cpu_x86_bind(struct udevice *dev);
+
+/**
+ * cpu_x86_get_desc() - Get a description string for an x86 CPU
+ *
+ * This uses cpu_get_name() and is suitable to use as the get_desc() method for
+ * the CPU uclass.
+ *
+ * @dev:	Device to check (UCLASS_CPU)
+ * @buf:	Buffer to place string
+ * @size:	Size of string space
+ * @return:	0 if OK, -ENOSPC if buffer is too small, other -ve on error
+ */
+int cpu_x86_get_desc(struct udevice *dev, char *buf, int size);
+
+#endif /* _ASM_CPU_X86_H */
Signature · 1 line
1.8.2.1
#5 lore raw

PATCH v2 3/9 x86: dm: Clean up cpu drivers

Quoted 16 lines · Bin Meng

This commit does the following to clean up x86 cpu dm drivers:
- Move cpu_x86 driver codes from arch/x86/cpu/cpu.c to a dedicated file arch/x86/cpu/cpu_x86.c
- Rename x86_cpu_get_desc() to cpu_x86_get_desc() to keep consistent naming with other dm drivers
- Add a new cpu_x86_bind() in the cpu_x86 driver which does exactly the same as the one in the intel baytrail cpu driver
- Update intel baytrail cpu driver to use cpu_x86_get_desc() and cpu_x86_bind()

Signed-off-by Bin Meng <[email protected]>
Acked-by Simon Glass <[email protected]>

---

Changes in v2: None

Quoted 9 lines
 arch/x86/cpu/Makefile          |  2 +-
 arch/x86/cpu/baytrail/cpu.c    | 15 +++----------
 arch/x86/cpu/cpu.c             | 28 ------------------------
 arch/x86/cpu/cpu_x86.c         | 48 ++++++++++++++++++++++++++++++++++++++++++
 arch/x86/include/asm/cpu.h     | 14 ------------
 arch/x86/include/asm/cpu_x86.h | 34 ++++++++++++++++++++++++++++++
 6 files changed, 86 insertions(+), 55 deletions(-)
 create mode 100644 arch/x86/cpu/cpu_x86.c
 create mode 100644 arch/x86/include/asm/cpu_x86.h

Applied to u-boot-x86.

author
#6 lore raw

PATCH v2 4/9 x86: Move MP initialization codes into a common place

In reply to a message not in the archive

Most of the MP initialization codes in arch/x86/cpu/baytrail/cpu.c is common to all x86 processors, except detect_num_cpus() which varies from cpu to cpu. Move these to arch/x86/cpu/cpu.c and declare a weak detect_num_cpus() which just returns 2 which is minimally required.

Signed-off-by Bin Meng <[email protected]>

---

Changes in v2: None

 arch/x86/cpu/baytrail/cpu.c | 44 +-----------------------------------------
 arch/x86/cpu/cpu.c          | 47 +++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 48 insertions(+), 43 deletions(-)
arch/x86/cpu/baytrail/cpu.c +1 -43
index 05156a5..7805056 100644
@@ -12,23 +12,11 @@
 #include <asm/cpu.h>
 #include <asm/cpu_x86.h>
 #include <asm/lapic.h>
-#include <asm/mp.h>
 #include <asm/msr.h>
 #include <asm/turbo.h>
 
 #ifdef CONFIG_SMP
-static int enable_smis(struct udevice *cpu, void *unused)
-{
-	return 0;
-}
-
-static struct mp_flight_record mp_steps[] = {
-	MP_FR_BLOCK_APS(mp_init_cpu, NULL, mp_init_cpu, NULL),
-	/* Wait for APs to finish initialization before proceeding. */
-	MP_FR_BLOCK_APS(NULL, NULL, enable_smis, NULL),
-};
-
-static int detect_num_cpus(void)
+int detect_num_cpus(void)
 {
 	int ecx = 0;
 

@@ -52,38 +40,8 @@ static int detect_num_cpus(void)
 		ecx++;
 	}
 }
-
-static int baytrail_init_cpus(void)
-{
-	struct mp_params mp_params;
-
-	lapic_setup();
-
-	mp_params.num_cpus = detect_num_cpus();
-	mp_params.parallel_microcode_load = 0,
-	mp_params.flight_plan = &mp_steps[0];
-	mp_params.num_records = ARRAY_SIZE(mp_steps);
-	mp_params.microcode_pointer = 0;
-
-	if (mp_init(&mp_params)) {
-		printf("Warning: MP init failure\n");
-		return -EIO;
-	}
-
-	return 0;
-}
 #endif
 
-int x86_init_cpus(void)
-{
-#ifdef CONFIG_SMP
-	debug("Init additional CPUs\n");
-	baytrail_init_cpus();
-#endif
-
-	return 0;
-}
-
 static void set_max_freq(void)
 {
 	msr_t perf_ctl;
arch/x86/cpu/cpu.c +47 -0

65 lines not on this page · raw message

Signature · 1 line
1.8.2.1
author
#7 lore raw

PATCH v2 5/9 x86: kconfig: Make MAX_CPUS and AP_STACK_SIZE depend on SMP

In reply to a message not in the archive

MAX_CPUS and AP_STACK_SIZE are only meaningful when SMP is on.

Signed-off-by Bin Meng <[email protected]>
Acked-by Simon Glass <[email protected]>

---

Changes in v2: None

 arch/x86/Kconfig | 2 ++
 1 file changed, 2 insertions(+)
arch/x86/Kconfig +2 -0
index 3506ba2..d4cd9ed 100644
@@ -228,6 +228,7 @@ config FSP_TEMP_RAM_ADDR
 
 config MAX_CPUS
         int "Maximum number of CPUs permitted"
+        depends on SMP
         default 4
         help
           When using multi-CPU chips it is possible for U-Boot to start up

@@ -249,6 +250,7 @@ config SMP
 
 config AP_STACK_SIZE
 	hex
+	depends on SMP
 	default 0x1000
 	help
 	  Each additional CPU started by U-Boot requires its own stack. This
Signature · 1 line
1.8.2.1
author
#9 lore raw

PATCH v2 6/9 x86: kconfig: Fix minor nits in MAX_CPUS

In reply to a message not in the archive

Move MAX_CPUS definition after SMP so that it shows below SMP in the menuconfig. Also replace the leading spaces in the MAX_CPUS section with tabs to conform coding standard.

Signed-off-by Bin Meng <[email protected]>
Acked-by Simon Glass <[email protected]>

---

Changes in v2: None

 arch/x86/Kconfig | 24 ++++++++++++------------
 1 file changed, 12 insertions(+), 12 deletions(-)
arch/x86/Kconfig +12 -12
index d4cd9ed..4757011 100644
@@ -226,18 +226,6 @@ config FSP_TEMP_RAM_ADDR
 	  Stack top address which is used in FspInit after DRAM is ready and
 	  CAR is disabled.
 
-config MAX_CPUS
-        int "Maximum number of CPUs permitted"
-        depends on SMP
-        default 4
-        help
-          When using multi-CPU chips it is possible for U-Boot to start up
-          more than one CPU. The stack memory used by all of these CPUs is
-          pre-allocated so at present U-Boot wants to know the maximum
-          number of CPUs that may be present. Set this to at least as high
-          as the number of CPUs in your system (it uses about 4KB of RAM for
-          each CPU).
-
 config SMP
 	bool "Enable Symmetric Multiprocessing"
 	default n

@@ -248,6 +236,18 @@ config SMP
 	  only one CPU will be enabled regardless of the number of CPUs
 	  available.
 
+config MAX_CPUS
+	int "Maximum number of CPUs permitted"
+	depends on SMP
+	default 4
+	help
+	  When using multi-CPU chips it is possible for U-Boot to start up
+	  more than one CPU. The stack memory used by all of these CPUs is
+	  pre-allocated so at present U-Boot wants to know the maximum
+	  number of CPUs that may be present. Set this to at least as high
+	  as the number of CPUs in your system (it uses about 4KB of RAM for
+	  each CPU).
+
 config AP_STACK_SIZE
 	hex
 	depends on SMP
Signature · 1 line
1.8.2.1
#10 lore raw

PATCH v2 6/9 x86: kconfig: Fix minor nits in MAX_CPUS

Quoted 4 lines · Bin Meng

Move MAX_CPUS definition after SMP so that it shows below SMP in the menuconfig. Also replace the leading spaces in the MAX_CPUS section with tabs to conform coding standard.

Quoted 8 lines
Signed-off-by Bin Meng <[email protected]>
Acked-by Simon Glass <[email protected]>

---

Changes in v2: None

 arch/x86/Kconfig | 24 ++++++++++++------------
 1 file changed, 12 insertions(+), 12 deletions(-)

Applied to u-boot-x86.

author
#11 lore raw

PATCH v2 7/9 x86: Move lapic_setup() call into init_bsp()

In reply to a message not in the archive

Currently lapic_setup() is called before calling mp_init(), which then calls init_bsp() where it calls enable_lapic(), which was already enabled in lapic_setup(). Hence move lapic_setup() call into init_bsp() to avoid the duplication.

Signed-off-by Bin Meng <[email protected]>
Acked-by Simon Glass <[email protected]>

---

Changes in v2: None

 arch/x86/cpu/cpu.c     | 2 --
 arch/x86/cpu/mp_init.c | 2 +-
 2 files changed, 1 insertion(+), 3 deletions(-)
arch/x86/cpu/cpu.c +0 -2
index ddc7dc3..dd1b18b 100644
@@ -626,8 +626,6 @@ static int x86_mp_init(void)
 {
 	struct mp_params mp_params;
 
-	lapic_setup();
-
 	mp_params.num_cpus = detect_num_cpus();
 	mp_params.parallel_microcode_load = 0,
 	mp_params.flight_plan = &mp_steps[0];
arch/x86/cpu/mp_init.c +1 -1
index ac5753a..864eb63 100644
@@ -415,7 +415,7 @@ static int init_bsp(struct udevice **devp)
 	cpu_get_name(processor_name);
 	debug("CPU: %s.\n", processor_name);
 
-	enable_lapic();
+	lapic_setup();
 
 	apic_id = lapicid();
 	ret = find_cpu_by_apid_id(apic_id, devp);
Signature · 1 line
1.8.2.1
author
#12 lore raw

PATCH v2 8/9 x86: Clean up lapic codes

In reply to a message not in the archive

This commit cleans up the lapic codes:
- Delete arch/x86/include/asm/lapic_def.h, and move register and bit defines into arch/x86/include/asm/lapic.h
- Use MSR defines from msr-index.h in enable_lapic() and disable_lapic()
- Remove unnecessary stuff like NEED_LAPIC, X86_GOOD_APIC and CONFIG_AP_IN_SIPI_WAIT
- Move struct x86_cpu_priv defines to asm/arch-ivybridge/bd82x6x.h, as it is not apic related and only used by ivybridge
- Fix coding convention issues

Signed-off-by Bin Meng <[email protected]>
Acked-by Simon Glass <[email protected]>

---

Changes in v2: None

 arch/x86/cpu/ivybridge/model_206ax.c          |   2 +-
 arch/x86/cpu/lapic.c                          |  38 ++++----
 arch/x86/include/asm/arch-ivybridge/bd82x6x.h |  14 ++-
 arch/x86/include/asm/lapic.h                  | 131 ++++++++++++++------------
 arch/x86/include/asm/lapic_def.h              | 101 --------------------
 5 files changed, 103 insertions(+), 183 deletions(-)
 delete mode 100644 arch/x86/include/asm/lapic_def.h
arch/x86/cpu/ivybridge/model_206ax.c +1 -1
index 8b08c40..fd7db97 100644
@@ -13,12 +13,12 @@
 #include <asm/acpi.h>
 #include <asm/cpu.h>
 #include <asm/lapic.h>
-#include <asm/lapic_def.h>
 #include <asm/msr.h>
 #include <asm/mtrr.h>
 #include <asm/processor.h>
 #include <asm/speedstep.h>
 #include <asm/turbo.h>
+#include <asm/arch/bd82x6x.h>
 #include <asm/arch/model_206ax.h>
 
 static void enable_vmx(void)
arch/x86/cpu/lapic.c +17 -21
index 4690603..6769ae5 100644
@@ -8,50 +8,46 @@
  */
 
 #include <common.h>
-#include <asm/msr.h>
-#include <asm/io.h>
 #include <asm/lapic.h>
 #include <asm/post.h>
 
 void lapic_setup(void)
 {
-#if NEED_LAPIC == 1
+#ifdef CONFIG_SMP
 	/* Only Pentium Pro and later have those MSR stuff */
 	debug("Setting up local apic: ");
 
 	/* Enable the local apic */
 	enable_lapic();
 
-	/*
-	 * Set Task Priority to 'accept all'.
-	 */
+	/* Set Task Priority to 'accept all' */
 	lapic_write_around(LAPIC_TASKPRI,
 			   lapic_read_around(LAPIC_TASKPRI) & ~LAPIC_TPRI_MASK);
 
 	/* Put the local apic in virtual wire mode */
 	lapic_write_around(LAPIC_SPIV, (lapic_read_around(LAPIC_SPIV) &
-				~(LAPIC_VECTOR_MASK)) | LAPIC_SPIV_ENABLE);
+			   ~(LAPIC_VECTOR_MASK)) | LAPIC_SPIV_ENABLE);
 	lapic_write_around(LAPIC_LVT0, (lapic_read_around(LAPIC_LVT0) &
-			~(LAPIC_LVT_MASKED | LAPIC_LVT_LEVEL_TRIGGER |
-			  LAPIC_LVT_REMOTE_IRR | LAPIC_INPUT_POLARITY |
-			  LAPIC_SEND_PENDING | LAPIC_LVT_RESERVED_1 |
-			  LAPIC_DELIVERY_MODE_MASK)) |
-			(LAPIC_LVT_REMOTE_IRR | LAPIC_SEND_PENDING |
-			 LAPIC_DELIVERY_MODE_EXTINT));
+			   ~(LAPIC_LVT_MASKED | LAPIC_LVT_LEVEL_TRIGGER |
+			   LAPIC_LVT_REMOTE_IRR | LAPIC_INPUT_POLARITY |
+			   LAPIC_SEND_PENDING | LAPIC_LVT_RESERVED_1 |
+			   LAPIC_DELIVERY_MODE_MASK)) |
+			   (LAPIC_LVT_REMOTE_IRR | LAPIC_SEND_PENDING |
+			   LAPIC_DELIVERY_MODE_EXTINT));
 	lapic_write_around(LAPIC_LVT1, (lapic_read_around(LAPIC_LVT1) &
-			~(LAPIC_LVT_MASKED | LAPIC_LVT_LEVEL_TRIGGER |
-			  LAPIC_LVT_REMOTE_IRR | LAPIC_INPUT_POLARITY |
-			  LAPIC_SEND_PENDING | LAPIC_LVT_RESERVED_1 |
-			  LAPIC_DELIVERY_MODE_MASK)) |
-		(LAPIC_LVT_REMOTE_IRR | LAPIC_SEND_PENDING |
-			LAPIC_DELIVERY_MODE_NMI));
+			   ~(LAPIC_LVT_MASKED | LAPIC_LVT_LEVEL_TRIGGER |
+			   LAPIC_LVT_REMOTE_IRR | LAPIC_INPUT_POLARITY |
+			   LAPIC_SEND_PENDING | LAPIC_LVT_RESERVED_1 |
+			   LAPIC_DELIVERY_MODE_MASK)) |
+			   (LAPIC_LVT_REMOTE_IRR | LAPIC_SEND_PENDING |
+			   LAPIC_DELIVERY_MODE_NMI));
 
 	debug("apic_id: 0x%02lx, ", lapicid());
-#else /* !NEED_LLAPIC */
+#else /* !CONFIG_SMP */
 	/* Only Pentium Pro and later have those MSR stuff */
 	debug("Disabling local apic: ");
 	disable_lapic();
-#endif /* !NEED_LAPIC */
+#endif /* CONFIG_SMP */
 	debug("done.\n");
 	post_code(POST_LAPIC);
 }
arch/x86/include/asm/arch-ivybridge/bd82x6x.h +13 -1
index 5ae32f7..7786493 100644
@@ -16,7 +16,19 @@ int gma_func0_init(pci_dev_t dev, struct pci_controller *hose,
 		   const void *blob, int node);
 int bd82x6x_init(void);
 
-struct x86_cpu_priv;
+/**
+ * struct x86_cpu_priv - Information about a single CPU
+ *
+ * @apic_id: Advanced Programmable Interrupt Controller Identifier, which is
+ * just a number representing the CPU core
+ *
+ * TODO: Move this to driver model once lifecycle is understood
+ */
+struct x86_cpu_priv {
+	int apic_id;
+	int start_err;
+};
+
 int model_206ax_init(struct x86_cpu_priv *cpu);
 
 #endif
arch/x86/include/asm/lapic.h +72 -59

199 lines not on this page · raw message

arch/x86/include/asm/lapic_def.h deleted +0 -101

101 lines not on this page · raw message

Signature · 1 line
1.8.2.1
author
#13 lore raw

PATCH v2 9/9 x86: crownbay: Add MP initialization

In reply to a message not in the archive

Intel Crown Bay board has a TunnelCreek processor which supports hyper-threading. Add /cpus node in the crownbay.dts and enable the MP initialization.

Signed-off-by Bin Meng <[email protected]>
Acked-by Simon Glass <[email protected]>

---

Changes in v2:
- Move CONFIG_MAX_CPUS after CONFIG_SMP in crownbay_defconfig to match the order in Kconfig

 arch/x86/dts/crownbay.dts  | 20 ++++++++++++++++++++
 configs/crownbay_defconfig |  4 ++++
 2 files changed, 24 insertions(+)
arch/x86/dts/crownbay.dts +20 -0
index d68efda..1ec90cd 100644
@@ -23,6 +23,26 @@
 		silent_console = <0>;
 	};
 
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu at 0 {
+			device_type = "cpu";
+			compatible = "cpu-x86";
+			reg = <0>;
+			intel,apic-id = <0>;
+		};
+
+		cpu at 1 {
+			device_type = "cpu";
+			compatible = "cpu-x86";
+			reg = <1>;
+			intel,apic-id = <1>;
+		};
+
+	};
+
 	gpioa {
 		compatible = "intel,ich6-gpio";
 		u-boot,dm-pre-reloc;
configs/crownbay_defconfig +4 -0
index d3a370d..d21177d 100644
@@ -2,6 +2,10 @@ CONFIG_X86=y
 CONFIG_VENDOR_INTEL=y
 CONFIG_DEFAULT_DEVICE_TREE="crownbay"
 CONFIG_TARGET_CROWNBAY=y
+CONFIG_SMP=y
+CONFIG_MAX_CPUS=2
 CONFIG_GENERATE_PIRQ_TABLE=y
+CONFIG_CMD_CPU=y
 CONFIG_CMD_NET=y
 CONFIG_OF_CONTROL=y
+CONFIG_CPU=y
Signature · 1 line
1.8.2.1