Patch "x86: bpf_jit: fix FROM_BE16 and FROM_LE16/32 instructions" has been added to the 4.0-stable tree

This is a note to let you know that I've just added the patch titled

x86: bpf_jit: fix FROM_BE16 and FROM_LE16/32 instructions

to the 4.0-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:

     x86-bpf_jit-fix-from_be16-and-from_le16-32-instructions.patch

and it can be found in the queue-4.0 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree, please let <[email protected]> know about it.

From: Alexei Starovoitov <[email protected]>
Date: Mon, 11 May 2015 23:25:16 -0700
Subject: x86: bpf_jit: fix FROM_BE16 and FROM_LE16/32 instructions

From: Alexei Starovoitov <[email protected]>

[ Upstream commit 343f845b375989f1753f605902931fa939aa2223 ]

FROM_BE16:
'ror %reg, 8' doesn't clear upper bits of the register, so use additional 'movzwl' insn to zero extend 16 bits into 64

FROM_LE16:
should zero extend lower 16 bits into 64 bit

FROM_LE32:
should zero extend lower 32 bits into 64 bit

---
 arch/x86/net/bpf_jit_comp.c |   28 ++++++++++++++++++++++++++++
 1 file changed, 28 insertions(+)

@@ -559,6 +559,13 @@ static int do_jit(struct bpf_prog *bpf_p
 				if (is_ereg(dst_reg))
 					EMIT1(0x41);
 				EMIT3(0xC1, add_1reg(0xC8, dst_reg), 8);
+
+				/* emit 'movzwl eax, ax' */
+				if (is_ereg(dst_reg))
+					EMIT3(0x45, 0x0F, 0xB7);
+				else
+					EMIT2(0x0F, 0xB7);
+				EMIT1(add_2reg(0xC0, dst_reg, dst_reg));
 				break;
 			case 32:
 				/* emit 'bswap eax' to swap lower 4 bytes */

@@ -577,6 +584,27 @@ static int do_jit(struct bpf_prog *bpf_p
 			break;
 
 		case BPF_ALU | BPF_END | BPF_FROM_LE:
+			switch (imm32) {
+			case 16:
+				/* emit 'movzwl eax, ax' to zero extend 16-bit
+				 * into 64 bit
+				 */
+				if (is_ereg(dst_reg))
+					EMIT3(0x45, 0x0F, 0xB7);
+				else
+					EMIT2(0x0F, 0xB7);
+				EMIT1(add_2reg(0xC0, dst_reg, dst_reg));
+				break;
+			case 32:
+				/* emit 'mov eax, eax' to clear upper 32-bits */
+				if (is_ereg(dst_reg))
+					EMIT1(0x45);
+				EMIT2(0x89, add_2reg(0xC0, dst_reg, dst_reg));
+				break;
+			case 64:
+				/* nop */
+				break;
+			}
 			break;
 
 			/* ST: *(u8*)(dst_reg + off) = imm */

Patches currently in stable-queue which might be from [email protected] are

queue-4.0/x86-bpf_jit-fix-from_be16-and-from_le16-32-instructions.patch queue-4.0/x86-bpf_jit-fix-compilation-of-large-bpf-programs.patch queue-4.0/net-sched-fix-call_rcu-race-on-classifier-module-unloads.patch