arm: mvebu: Enable USB EHCI support on Armada XP

PATCH New Stefan Roese 2 participants 4 messages Jul 23, 2015

Subsystems (5)

Arm (32-bit) USB Arm sub-architectures Arm/Marvell Kirkwood and Armada 370, 375, 38x, 39x, XP, 3700, 7K/8K, CN9130 SoC support +1 more subsystems

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Stefan Roese

author

2015-07-23 11:02 UTC #0 lore raw

PATCH v2 9/10 arm: mvebu: Enable USB EHCI support on Armada XP

This patch enables the USB EHCI support for the Marvell Armada XP (AXP) SoCs. In compatism to the Armada 38x (A38x), the AXP needs to configure the USB PLL and the USB PHY's specifically in U-Boot. The A38x has done this already in the bin_hdr (SPL U-Boot). Without this, accessing the controller registers in U-Boot or Linux will hang the CPU.

Additionally, the AXP uses a different USB EHCI base address. This patch also takes care of this by runtime SoC detection in the Marvell EHCI driver.

Signed-off-by Stefan Roese <[email protected]>

Signed-off-by Anton Schubert <[email protected]>

Cc Marek Vasut <[email protected]>

Cc Luka Perkov <[email protected]>

---
v2:
- Use clrsetbits_le32() as suggested by Marek
- Use additional bracket in macro as suggested by Marek

 arch/arm/mach-mvebu/cpu.c              | 43 ++++++++++++++++++++++++++++++++++
 arch/arm/mach-mvebu/include/mach/soc.h |  1 +
 drivers/usb/host/ehci-marvell.c        |  9 ++++++-
 3 files changed, 52 insertions(+), 1 deletion(-)

arch/arm/mach-mvebu/cpu.c +43 -0

index 38e15aa..1c5f4c3 100644
@@ -179,6 +179,46 @@ static void set_cbar(u32 addr)
 	asm("mcr p15, 4, %0, c15, c0" : : "r" (addr));
 }
 
+#define MV_USB_PHY_BASE			(MVEBU_AXP_USB_BASE + 0x800)
+#define MV_USB_PHY_PLL_REG(reg)		(MV_USB_PHY_BASE | (((reg) & 0xF) << 2))
+#define MV_USB_X3_BASE(addr)		(MVEBU_AXP_USB_BASE | BIT(11) | \
+					 (((addr) & 0xF) << 6))
+#define MV_USB_X3_PHY_CHANNEL(dev, reg)	(MV_USB_X3_BASE((dev) + 1) |	\
+					 (((reg) & 0xF) << 2))
+
+static void setup_usb_phys(void)
+{
+	int dev;
+
+	/*
+	 * USB PLL init
+	 */
+
+	/* Setup PLL frequency */
+	/* USB REF frequency = 25 MHz */
+	clrsetbits_le32(MV_USB_PHY_PLL_REG(1), 0x3ff, 0x605);
+
+	/* Power up PLL and PHY channel */
+	clrsetbits_le32(MV_USB_PHY_PLL_REG(2), 0, BIT(9));
+
+	/* Assert VCOCAL_START */
+	clrsetbits_le32(MV_USB_PHY_PLL_REG(1), 0, BIT(21));
+
+	mdelay(1);
+
+	/*
+	 * USB PHY init (change from defaults) specific for 40nm (78X30 78X60)
+	 */
+
+	for (dev = 0; dev < 3; dev++) {
+		clrsetbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 3), 0, BIT(15));
+
+		/* Assert REG_RCAL_START in channel REG 1 */
+		clrsetbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 1), 0, BIT(12));
+		udelay(40);
+		clrsetbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 1), BIT(12), 0);
+	}
+}
 
 int arch_cpu_init(void)
 {

@@ -246,6 +286,9 @@ int arch_cpu_init(void)
 		clrsetbits_le32(ARMADA_XP_PUP_ENABLE, 0,
 				GE0_PUP_EN | GE1_PUP_EN | LCD_PUP_EN |
 				NAND_PUP_EN | SPI_PUP_EN);
+
+		/* Configure USB PLL and PHYs on AXP */
+		setup_usb_phys();
 	}
 
 	/* Enable NAND and NAND arbiter */

arch/arm/mach-mvebu/include/mach/soc.h +1 -0

index 6115d6e..a8a6b27 100644
@@ -65,6 +65,7 @@
 #define MVEBU_EGIGA2_BASE	(MVEBU_REGISTER(0x30000))
 #define MVEBU_EGIGA3_BASE	(MVEBU_REGISTER(0x34000))
 #define MVEBU_REG_PCIE_BASE	(MVEBU_REGISTER(0x40000))
+#define MVEBU_AXP_USB_BASE      (MVEBU_REGISTER(0x50000))
 #define MVEBU_USB20_BASE	(MVEBU_REGISTER(0x58000))
 #define MVEBU_EGIGA0_BASE	(MVEBU_REGISTER(0x70000))
 #define MVEBU_EGIGA1_BASE	(MVEBU_REGISTER(0x74000))

drivers/usb/host/ehci-marvell.c +8 -1

index 03c489c..826e7f7 100644
@@ -33,7 +33,14 @@ DECLARE_GLOBAL_DATA_PTR;
  */
 #ifdef CONFIG_ARMADA_XP
 
-#define MVUSB0_BASE		MVEBU_USB20_BASE
+/*
+ * Armada XP and Armada 38x have different base addresses for
+ * the USB 2.0 EHCI host controller. So we need to provide
+ * a mechnism to support both here.
+ */
+#define MVUSB0_BASE					\
+	(mvebu_soc_family() == MVEBU_SOC_A38X ?		\
+	 MVEBU_USB20_BASE : MVEBU_AXP_USB_BASE)
 
 /*
  * Once all the older Marvell SoC's (Orion, Kirkwood) are converted

Signature · 1 line

2.4.6

Marek Vasut

2015-07-23 14:17 UTC #1 lore raw

PATCH v2 9/10 arm: mvebu: Enable USB EHCI support on Armada XP

Quoted 9 lines · Stefan Roese

This patch enables the USB EHCI support for the Marvell Armada XP (AXP) SoCs. In compatism to the Armada 38x (A38x), the AXP needs to configure the USB PLL and the USB PHY's specifically in U-Boot. The A38x has done this already in the bin_hdr (SPL U-Boot). Without this, accessing the controller registers in U-Boot or Linux will hang the CPU.
Additionally, the AXP uses a different USB EHCI base address. This patch also takes care of this by runtime SoC detection in the Marvell EHCI driver.

[...]

drivers/usb/host/ehci-marvell.c DECLARE_GLOBAL_DATA_PTR; · line 39

Quoted 13 lines

(quoted diff) +0 -0

b/drivers/usb/host/ehci-marvell.c index 03c489c..826e7f7 100644

drivers/usb/host/ehci-marvell.c +4 -1

@@ -33,7 +33,14 @@ DECLARE_GLOBAL_DATA_PTR;
  */
 #ifdef CONFIG_ARMADA_XP
 
-#define MVUSB0_BASE		MVEBU_USB20_BASE
+/*
+ * Armada XP and Armada 38x have different base addresses for
+ * the USB 2.0 EHCI host controller. So we need to provide
+ * a mechnism to support both here.

mechanism (I can fix that myself)

drivers/usb/host/ehci-marvell.c DECLARE_GLOBAL_DATA_PTR; · line 46

Quoted 7 lines

drivers/usb/host/ehci-marvell.c +4 -0

+ */
+#define MVUSB0_BASE					\
+	(mvebu_soc_family() == MVEBU_SOC_A38X ?		\
+	 MVEBU_USB20_BASE : MVEBU_AXP_USB_BASE)
 
 /*
  * Once all the older Marvell SoC's (Orion, Kirkwood) are converted

Do you want me to pick this via USB tree ?

Best regards,
Marek Vasut

Stefan Roese

author

2015-07-23 14:53 UTC #2 lore raw

PATCH v2 9/10 arm: mvebu: Enable USB EHCI support on Armada XP

Quoted 34 lines · Marek Vasut

Quoted 9 lines · Stefan Roese
This patch enables the USB EHCI support for the Marvell Armada XP (AXP) SoCs. In compatism to the Armada 38x (A38x), the AXP needs to configure the USB PLL and the USB PHY's specifically in U-Boot. The A38x has done this already in the bin_hdr (SPL U-Boot). Without this, accessing the controller registers in U-Boot or Linux will hang the CPU.
Additionally, the AXP uses a different USB EHCI base address. This patch also takes care of this by runtime SoC detection in the Marvell EHCI driver.
[...]
drivers/usb/host/ehci-marvell.c DECLARE_GLOBAL_DATA_PTR; · line 39
Quoted 13 lines
(quoted diff) +0 -0
b/drivers/usb/host/ehci-marvell.c index 03c489c..826e7f7 100644
drivers/usb/host/ehci-marvell.c +4 -1
@@ -33,7 +33,14 @@ DECLARE_GLOBAL_DATA_PTR;
   */
  #ifdef CONFIG_ARMADA_XP
 
-#define MVUSB0_BASE		MVEBU_USB20_BASE
+/*
+ * Armada XP and Armada 38x have different base addresses for
+ * the USB 2.0 EHCI host controller. So we need to provide
+ * a mechnism to support both here.
mechanism (I can fix that myself)
Quoted 5 lines
drivers/usb/host/ehci-marvell.c +4 -0
+ */
+#define MVUSB0_BASE					\
+	(mvebu_soc_family() == MVEBU_SOC_A38X ?		\
+	 MVEBU_USB20_BASE : MVEBU_AXP_USB_BASE)
 

Quoted 4 lines

drivers/usb/host/ehci-marvell.c DECLARE_GLOBAL_DATA_PTR; · line 46
Quoted 2 lines
drivers/usb/host/ehci-marvell.c +0 -0
  /*
   * Once all the older Marvell SoC's (Orion, Kirkwood) are converted
Do you want me to pick this via USB tree ?

If you have no objections, then it would be easer if Luka pushes all patches together. Since there might be conflicts in the arch/arm/ files otherwise.

Thanks,
Stefan

Marek Vasut

2015-07-23 15:00 UTC #3 lore raw

PATCH v2 9/10 arm: mvebu: Enable USB EHCI support on Armada XP

Quoted 39 lines · Stefan Roese

Quoted 38 lines · Marek Vasut
Quoted 9 lines · Stefan Roese
This patch enables the USB EHCI support for the Marvell Armada XP (AXP) SoCs. In compatism to the Armada 38x (A38x), the AXP needs to configure the USB PLL and the USB PHY's specifically in U-Boot. The A38x has done this already in the bin_hdr (SPL U-Boot). Without this, accessing the controller registers in U-Boot or Linux will hang the CPU.
Additionally, the AXP uses a different USB EHCI base address. This patch also takes care of this by runtime SoC detection in the Marvell EHCI driver.
[...]
Quoted 5 lines
(quoted diff) +0 -0
b/drivers/usb/host/ehci-marvell.c index 03c489c..826e7f7 100644
drivers/usb/host/ehci-marvell.c DECLARE_GLOBAL_DATA_PTR; · line 41
Quoted 10 lines
drivers/usb/host/ehci-marvell.c +4 -1
@@ -33,7 +33,14 @@ DECLARE_GLOBAL_DATA_PTR;
 
   */
 
  #ifdef CONFIG_ARMADA_XP
 
-#define MVUSB0_BASE		MVEBU_USB20_BASE
+/*
+ * Armada XP and Armada 38x have different base addresses for
+ * the USB 2.0 EHCI host controller. So we need to provide
+ * a mechnism to support both here.
mechanism (I can fix that myself)
Quoted 7 lines
drivers/usb/host/ehci-marvell.c +4 -0
+ */
+#define MVUSB0_BASE					\
+	(mvebu_soc_family() == MVEBU_SOC_A38X ?		\
+	 MVEBU_USB20_BASE : MVEBU_AXP_USB_BASE)
 
/*

Quoted 7 lines

Quoted 3 lines
Quoted 1 line
* Once all the older Marvell SoC's (Orion, Kirkwood) are converted
Do you want me to pick this via USB tree ?
If you have no objections, then it would be easer if Luka pushes all patches together. Since there might be conflicts in the arch/arm/ files otherwise.

OK!

Best regards,
Marek Vasut