FAILED: patch "[PATCH] dmaengine: at_xdmac: fix transfer data width in" failed to apply to 4.1-stable tree

[email protected]

author maintainer

2015-08-10 21:27 UTC #0 lore raw

The patch below does not apply to the 4.1-stable tree.
If someone wants it applied there, or to any other stable or longterm tree, then please email the backport, including the original git commit id to <[email protected]>.

thanks,

greg k-h

------------------ original commit in Linus's tree ------------------

Quoted 1 line

From 1c8a38b1268aebc1a903b21b11575077e02d2cf7 Mon Sep 17 00:00:00 2001

From: Cyrille Pitchen <[email protected]>
Date: Tue, 30 Jun 2015 14:36:57 +0200
Subject: [PATCH] dmaengine: at_xdmac: fix transfer data width in
at_xdmac_prep_slave_sg()

This patch adds the missing update of the transfer data width in at_xdmac_prep_slave_sg().

Indeed, for each item in the scatter-gather list, we check whether the transfer length is aligned with the data width provided by dmaengine_slave_config(). If so, we directly use this data width for the current part of the transfer we are preparing. Otherwise, the data width is reduced to 8 bits (1 byte). Of course, the actual number of register accesses must also be updated to match the new data width.

So one chunk was missing in the original patch (see Fixes tag below): the number of register accesses was correctly set to (len >> fixed_dwidth) in mbr_ubc but the real data width was not updated in mbr_cfg. Since mbr_cfg may change for each part of the scatter-gather transfer this also explains why the original patch used the Descriptor View 2 instead of the Descriptor View 1.

Let's take the example of a DMA transfer to write 8bit data into an Atmel USART with FIFOs. When FIFOs are enabled in the USART, its Transmit Holding Register (THR) works in multidata mode, that is to say that up to 4 8bit data can be written into the THR in a single 32bit access and it is still possible to write only one data with a 8bit access. To take advantage of this new feature, the DMA driver was modified to allow multiple dwidths when doing slave transfers.
For instance, when the total length is 22 bytes, the USART driver splits the transfer into 2 parts:

First part: 20 bytes transferred through 5 32bit writes into THR Second part: 2 bytes transferred though 2 8bit writes into THR

For the second part, the data width was first set to 4_BYTES by the USART driver thanks to dmaengine_slave_config() then at_xdmac_prep_slave_sg() reduces this data width to 1_BYTE because the 2 byte length is not aligned with the original 4_BYTES data width. Since the data width is modified, the actual number of writes into THR must be set accordingly.

Signed-off-by Cyrille Pitchen <[email protected]>

Fixes 6d3a7d9e3ada ("dmaengine: at_xdmac: allow muliple dwidths when doing slave transfers")

Cc [email protected] #4.0 and later

Acked-by Nicolas Ferre <[email protected]>

Acked-by Ludovic Desroches <[email protected]>

Signed-off-by Vinod Koul <[email protected]>

drivers/dma/at_xdmac.c +4 -3

index 52ca1ccefa3f..40afa2a16cfc 100644
@@ -682,15 +682,16 @@ at_xdmac_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
 			desc->lld.mbr_sa = mem;
 			desc->lld.mbr_da = atchan->sconfig.dst_addr;
 		}
-		desc->lld.mbr_cfg = atchan->cfg;
-		dwidth = at_xdmac_get_dwidth(desc->lld.mbr_cfg);
+		dwidth = at_xdmac_get_dwidth(atchan->cfg);
 		fixed_dwidth = IS_ALIGNED(len, 1 << dwidth)
-			       ? at_xdmac_get_dwidth(desc->lld.mbr_cfg)
+			       ? dwidth
 			       : AT_XDMAC_CC_DWIDTH_BYTE;
 		desc->lld.mbr_ubc = AT_XDMAC_MBR_UBC_NDV2			/* next descriptor view */
 			| AT_XDMAC_MBR_UBC_NDEN					/* next descriptor dst parameter update */
 			| AT_XDMAC_MBR_UBC_NSEN					/* next descriptor src parameter update */
 			| (len >> fixed_dwidth);				/* microblock length */
+		desc->lld.mbr_cfg = (atchan->cfg & ~AT_XDMAC_CC_DWIDTH_MASK) |
+				    AT_XDMAC_CC_DWIDTH(fixed_dwidth);
 		dev_dbg(chan2dev(chan),
 			 "%s: lld: mbr_sa=%pad, mbr_da=%pad, mbr_ubc=0x%08x\n",
 			 __func__, &desc->lld.mbr_sa, &desc->lld.mbr_da, desc->lld.mbr_ubc);

Ludovic Desroches

2015-08-11 09:09 UTC #1 lore raw

Hi Greg,

Quoted 2 lines · On Mon, Aug 10, 2015 at 02:27:56PM -0700, [email protected] wrote:

The patch below does not apply to the 4.1-stable tree.

I have tried to cherry-pick it on 4.1.4 and even on the fresh 4.1.5 and I have no conflict.

Can you tell me on top of which commit I have to pick this patch in order to get the conflict and fix it.

Quoted 8 lines

If someone wants it applied there, or to any other stable or longterm tree, then please email the backport, including the original git commit id to <[email protected]>.
thanks,
greg k-h

Thanks

Ludovic

Quoted 76 lines

------------------ original commit in Linus's tree ------------------
From 1c8a38b1268aebc1a903b21b11575077e02d2cf7 Mon Sep 17 00:00:00 2001
From: Cyrille Pitchen <[email protected]>
Date: Tue, 30 Jun 2015 14:36:57 +0200
Subject: [PATCH] dmaengine: at_xdmac: fix transfer data width in
at_xdmac_prep_slave_sg()
This patch adds the missing update of the transfer data width in at_xdmac_prep_slave_sg().
Indeed, for each item in the scatter-gather list, we check whether the transfer length is aligned with the data width provided by dmaengine_slave_config(). If so, we directly use this data width for the current part of the transfer we are preparing. Otherwise, the data width is reduced to 8 bits (1 byte). Of course, the actual number of register accesses must also be updated to match the new data width.
So one chunk was missing in the original patch (see Fixes tag below): the number of register accesses was correctly set to (len >> fixed_dwidth) in mbr_ubc but the real data width was not updated in mbr_cfg. Since mbr_cfg may change for each part of the scatter-gather transfer this also explains why the original patch used the Descriptor View 2 instead of the Descriptor View 1.
Let's take the example of a DMA transfer to write 8bit data into an Atmel USART with FIFOs. When FIFOs are enabled in the USART, its Transmit Holding Register (THR) works in multidata mode, that is to say that up to 4 8bit data can be written into the THR in a single 32bit access and it is still possible to write only one data with a 8bit access. To take advantage of this new feature, the DMA driver was modified to allow multiple dwidths when doing slave transfers.
For instance, when the total length is 22 bytes, the USART driver splits the transfer into 2 parts:
First part: 20 bytes transferred through 5 32bit writes into THR Second part: 2 bytes transferred though 2 8bit writes into THR
For the second part, the data width was first set to 4_BYTES by the USART driver thanks to dmaengine_slave_config() then at_xdmac_prep_slave_sg() reduces this data width to 1_BYTE because the 2 byte length is not aligned with the original 4_BYTES data width. Since the data width is modified, the actual number of writes into THR must be set accordingly.
Signed-off-by Cyrille Pitchen <[email protected]>
Fixes 6d3a7d9e3ada ("dmaengine: at_xdmac: allow muliple dwidths when doing slave transfers")
Cc [email protected] #4.0 and later
Acked-by Nicolas Ferre <[email protected]>
Acked-by Ludovic Desroches <[email protected]>
Signed-off-by Vinod Koul <[email protected]>
drivers/dma/at_xdmac.c +4 -3
index 52ca1ccefa3f..40afa2a16cfc 100644
@@ -682,15 +682,16 @@ at_xdmac_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
 			desc->lld.mbr_sa = mem;
 			desc->lld.mbr_da = atchan->sconfig.dst_addr;
 		}
-		desc->lld.mbr_cfg = atchan->cfg;
-		dwidth = at_xdmac_get_dwidth(desc->lld.mbr_cfg);
+		dwidth = at_xdmac_get_dwidth(atchan->cfg);
 		fixed_dwidth = IS_ALIGNED(len, 1 << dwidth)
-			       ? at_xdmac_get_dwidth(desc->lld.mbr_cfg)
+			       ? dwidth
 			       : AT_XDMAC_CC_DWIDTH_BYTE;
 		desc->lld.mbr_ubc = AT_XDMAC_MBR_UBC_NDV2			/* next descriptor view */
 			| AT_XDMAC_MBR_UBC_NDEN					/* next descriptor dst parameter update */
 			| AT_XDMAC_MBR_UBC_NSEN					/* next descriptor src parameter update */
 			| (len >> fixed_dwidth);				/* microblock length */
+		desc->lld.mbr_cfg = (atchan->cfg & ~AT_XDMAC_CC_DWIDTH_MASK) |
+				    AT_XDMAC_CC_DWIDTH(fixed_dwidth);
 		dev_dbg(chan2dev(chan),
 			 "%s: lld: mbr_sa=%pad, mbr_da=%pad, mbr_ubc=0x%08x\n",
 			 __func__, &desc->lld.mbr_sa, &desc->lld.mbr_da, desc->lld.mbr_ubc);

Greg KH

author maintainer

2015-08-11 22:41 UTC #2 lore raw

Quoted 11 lines · Ludovic Desroches

Hi Greg,
Quoted 2 lines · On Mon, Aug 10, 2015 at 02:27:56PM -0700, [email protected] wrote:
The patch below does not apply to the 4.1-stable tree.
I have tried to cherry-pick it on 4.1.4 and even on the fresh 4.1.5 and I have no conflict.
Can you tell me on top of which commit I have to pick this patch in order to get the conflict and fix it.

It doesn't apply for me on top of 4.1.5 with a simple 'patch' command:

	$ patch -p1 < ../dmaengine-at_xdmac-fix-transfer-data-width-in-at_xdmac_prep_slave_sg.patch 
	patching file drivers/dma/at_xdmac.c
	Hunk #1 FAILED at 682.
	1 out of 1 hunk FAILED -- saving rejects to file drivers/dma/at_xdmac.c.rej

How did 'cherry-pick' do it better? Can you send me the result of the git diff after 'cherry-pick' succeeded and I'll look to see what made it work properly...

thanks,

greg k-h

Ludovic Desroches

Acked-by Nicolas Ferre Acked-by

2015-08-12 07:05 UTC #3 lore raw

Quoted 14 lines · Greg KH

Quoted 11 lines · Ludovic Desroches
Hi Greg,
Quoted 2 lines · On Mon, Aug 10, 2015 at 02:27:56PM -0700, [email protected] wrote:
The patch below does not apply to the 4.1-stable tree.
I have tried to cherry-pick it on 4.1.4 and even on the fresh 4.1.5 and I have no conflict.
Can you tell me on top of which commit I have to pick this patch in order to get the conflict and fix it.
It doesn't apply for me on top of 4.1.5 with a simple 'patch' command:

Quoted 8 lines

	$ patch -p1 < ../dmaengine-at_xdmac-fix-transfer-data-width-in-at_xdmac_prep_slave_sg.patch 
	patching file drivers/dma/at_xdmac.c
	Hunk #1 FAILED at 682.
	1 out of 1 hunk FAILED -- saving rejects to file drivers/dma/at_xdmac.c.rej
How did 'cherry-pick' do it better? Can you send me the result of the git diff after 'cherry-pick' succeeded and I'll look to see what made it work properly...

It's not the first time I get this behavior.

$ git-log|head -n1
 352cb86  Linux 4.1.5  Greg Kroah-Hartman
$ git cherry-pick 1c8a38b1268a
[ludo/v4.1.5_xdmac 6807c71] dmaengine: at_xdmac: fix transfer data width
in at_xdmac_prep_slave_sg()
 Author: Cyrille Pitchen <[email protected]>
 Date: Tue Jun 30 14:36:57 2015 +0200
 1 file changed, 4 insertions(+), 3 deletions(-)

Patch attached.

Regards

Ludovic

commit 6807c714fe1e319bdb24e33684facddae7e3100b

Author: Cyrille Pitchen <[email protected]>
Date:   Tue Jun 30 14:36:57 2015 +0200

dmaengine: at_xdmac: fix transfer data width in at_xdmac_prep_slave_sg()

This patch adds the missing update of the transfer data width in at_xdmac_prep_slave_sg().

Indeed, for each item in the scatter-gather list, we check whether the transfer length is aligned with the data width provided by dmaengine_slave_config(). If so, we directly use this data width for the current part of the transfer we are preparing. Otherwise, the data width is reduced to 8 bits (1 byte). Of course, the actual number of register accesses must also be updated to match the new data width.

So one chunk was missing in the original patch (see Fixes tag below): the number of register accesses was correctly set to (len >> fixed_dwidth) in mbr_ubc but the real data width was not updated in mbr_cfg. Since mbr_cfg may change for each part of the scatter-gather transfer this also explains why the original patch used the Descriptor View 2 instead of the Descriptor View 1.

Let's take the example of a DMA transfer to write 8bit data into an Atmel USART with FIFOs. When FIFOs are enabled in the USART, its Transmit Holding Register (THR) works in multidata mode, that is to say that up to 4 8bit data can be written into the THR in a single 32bit access and it is still possible to write only one data with a 8bit access. To take advantage of this new feature, the DMA driver was modified to allow multiple dwidths when doing slave transfers.
For instance, when the total length is 22 bytes, the USART driver splits the transfer into 2 parts:

First part: 20 bytes transferred through 5 32bit writes into THR Second part: 2 bytes transferred though 2 8bit writes into THR

For the second part, the data width was first set to 4_BYTES by the USART driver thanks to dmaengine_slave_config() then at_xdmac_prep_slave_sg() reduces this data width to 1_BYTE because the 2 byte length is not aligned with the original 4_BYTES data width. Since the data width is modified, the actual number of writes into THR must be set accordingly.

Signed-off-by Cyrille Pitchen <[email protected]>

Fixes 6d3a7d9e3ada ("dmaengine: at_xdmac: allow muliple dwidths when doing slave transfers")

Cc [email protected] #4.0 and later

Acked-by Nicolas Ferre <[email protected]>

Acked-by Ludovic Desroches <[email protected]>

Signed-off-by Vinod Koul <[email protected]>

drivers/dma/at_xdmac.c +4 -3

index 7992164e..c89a7ab 100644
@@ -648,16 +648,17 @@ at_xdmac_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
 			desc->lld.mbr_sa = mem;
 			desc->lld.mbr_da = atchan->sconfig.dst_addr;
 		}
-		desc->lld.mbr_cfg = atchan->cfg;
-		dwidth = at_xdmac_get_dwidth(desc->lld.mbr_cfg);
+		dwidth = at_xdmac_get_dwidth(atchan->cfg);
 		fixed_dwidth = IS_ALIGNED(len, 1 << dwidth)
-			       ? at_xdmac_get_dwidth(desc->lld.mbr_cfg)
+			       ? dwidth
 			       : AT_XDMAC_CC_DWIDTH_BYTE;
 		desc->lld.mbr_ubc = AT_XDMAC_MBR_UBC_NDV2			/* next descriptor view */
 			| AT_XDMAC_MBR_UBC_NDEN					/* next descriptor dst parameter update */
 			| AT_XDMAC_MBR_UBC_NSEN					/* next descriptor src parameter update */
 			| (i == sg_len - 1 ? 0 : AT_XDMAC_MBR_UBC_NDE)		/* descriptor fetch */
 			| (len >> fixed_dwidth);				/* microblock length */
+		desc->lld.mbr_cfg = (atchan->cfg & ~AT_XDMAC_CC_DWIDTH_MASK) |
+				    AT_XDMAC_CC_DWIDTH(fixed_dwidth);
 		dev_dbg(chan2dev(chan),
 			 "%s: lld: mbr_sa=%pad, mbr_da=%pad, mbr_ubc=0x%08x\n",
 			 __func__, &desc->lld.mbr_sa, &desc->lld.mbr_da, desc->lld.mbr_ubc);

Greg KH

author maintainer

2015-08-13 21:12 UTC #4 lore raw

Quoted 35 lines · Ludovic Desroches

Quoted 14 lines · Greg KH
Quoted 11 lines · Ludovic Desroches
Hi Greg,
Quoted 2 lines · On Mon, Aug 10, 2015 at 02:27:56PM -0700, [email protected] wrote:
The patch below does not apply to the 4.1-stable tree.
I have tried to cherry-pick it on 4.1.4 and even on the fresh 4.1.5 and I have no conflict.
Can you tell me on top of which commit I have to pick this patch in order to get the conflict and fix it.
It doesn't apply for me on top of 4.1.5 with a simple 'patch' command:
Quoted 8 lines
	$ patch -p1 < ../dmaengine-at_xdmac-fix-transfer-data-width-in-at_xdmac_prep_slave_sg.patch 
	patching file drivers/dma/at_xdmac.c
	Hunk #1 FAILED at 682.
	1 out of 1 hunk FAILED -- saving rejects to file drivers/dma/at_xdmac.c.rej
How did 'cherry-pick' do it better? Can you send me the result of the git diff after 'cherry-pick' succeeded and I'll look to see what made it work properly...
It's not the first time I get this behavior.
$ git-log|head -n1
 352cb86  Linux 4.1.5  Greg Kroah-Hartman
$ git cherry-pick 1c8a38b1268a
[ludo/v4.1.5_xdmac 6807c71] dmaengine: at_xdmac: fix transfer data width
in at_xdmac_prep_slave_sg()
 Author: Cyrille Pitchen <[email protected]>
 Date: Tue Jun 30 14:36:57 2015 +0200
 1 file changed, 4 insertions(+), 3 deletions(-)

Quoted 1 line

Patch attached.

Thanks, now applied.

greg k-h

Ludovic Desroches

2015-08-14 08:02 UTC #5 lore raw

Quoted 2 lines · Greg KH

Quoted 1 line · Ludovic Desroches
On Tue, Aug 11, 2015 at 03:41:59PM -0700, Greg KH wrote:

[...]

Quoted 3 lines

Quoted 1 line
Patch attached.
Thanks, now applied.

Great, thanks.

Quoted 2 lines

greg k-h

Ludovic