Patch "i915: Set ddi_pll_sel in DP MST path" has been added to the 4.2-stable tree

This is a note to let you know that I've just added the patch titled

i915: Set ddi_pll_sel in DP MST path

to the 4.2-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:

     i915-set-ddi_pll_sel-in-dp-mst-path.patch

and it can be found in the queue-4.2 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree, please let <[email protected]> know about it.

From: Ander Conselvan de Oliveira <[email protected]>
Date: Mon, 31 Aug 2015 11:23:28 +0300
Subject: i915: Set ddi_pll_sel in DP MST path
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From: Ander Conselvan de Oliveira <[email protected]>

commit 6fa2d197936ba0b8936e813d0adecefac160062b upstream.

The DP MST encoder config function never sets ddi_pll_sel, even though its value is programmed in its ->pre_enable() hook. That used to work because a new pipe_config was kzalloc'ed at every modeset, and the value of zero selects the highest clock for the PLL. Starting with the commit below, the value of ddi_pll_sel is preserved through modesets, and since the correct value wasn't properly setup by the MST code, it could lead to warnings and blank screens.

commit 8504c74c7ae48b4b8ed1f1c0acf67482a7f45c93

Author: Ander Conselvan de Oliveira <[email protected]>
Date:   Fri May 15 11:51:50 2015 +0300

drm/i915: Preserve ddi_pll_sel when allocating new pipe_config

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91628

---
 drivers/gpu/drm/i915/intel_dp.c     |    2 +-
 drivers/gpu/drm/i915/intel_dp_mst.c |    5 +++++
 drivers/gpu/drm/i915/intel_drv.h    |    1 +
 3 files changed, 7 insertions(+), 1 deletion(-)

@@ -1134,7 +1134,7 @@ skl_edp_set_pll_config(struct intel_crtc
 	pipe_config->dpll_hw_state.ctrl1 = ctrl1;
 }
 
-static void
+void
 hsw_dp_set_ddi_pll_sel(struct intel_crtc_state *pipe_config)
 {
 	memset(&pipe_config->dpll_hw_state, 0,

@@ -33,6 +33,7 @@
 static bool intel_dp_mst_compute_config(struct intel_encoder *encoder,
 					struct intel_crtc_state *pipe_config)
 {
+	struct drm_device *dev = encoder->base.dev;
 	struct intel_dp_mst_encoder *intel_mst = enc_to_mst(&encoder->base);
 	struct intel_digital_port *intel_dig_port = intel_mst->primary;
 	struct intel_dp *intel_dp = &intel_dig_port->dp;

@@ -97,6 +98,10 @@ static bool intel_dp_mst_compute_config(
 			       &pipe_config->dp_m_n);
 
 	pipe_config->dp_m_n.tu = slots;
+
+	if (IS_HASWELL(dev) || IS_BROADWELL(dev))
+		hsw_dp_set_ddi_pll_sel(pipe_config);
+
 	return true;
 
 }

@@ -1194,6 +1194,7 @@ void intel_edp_drrs_disable(struct intel
 void intel_edp_drrs_invalidate(struct drm_device *dev,
 		unsigned frontbuffer_bits);
 void intel_edp_drrs_flush(struct drm_device *dev, unsigned frontbuffer_bits);
+void hsw_dp_set_ddi_pll_sel(struct intel_crtc_state *pipe_config);
 
 /* intel_dp_mst.c */
 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);

Patches currently in stable-queue which might be from [email protected] are

queue-4.2/i915-set-ddi_pll_sel-in-dp-mst-path.patch