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PCI: designware: Move LTSSM state definitions to pcie-designware.h

PATCH In review Fabio Estevam 3 participants 6 messages Oct 12, 2015 – Oct 21, 2015

Subsystems (2)
Arm i.MX and Layerscape PCI
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Fabio Estevam

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#0 lore raw

PATCH v3 1/3 PCI: designware: Move LTSSM state definitions to pcie-designware.h

From: Fabio Estevam <[email protected]>

Move LTSSM state definitions to common pcie-designware.h so that other drivers can make use of them.

Also, LTSSM states only use 5 bits so use 0x1f as its mask, so that we have a common LTSSM mask accross all PCIe designware drivers.

Keystone uses 5 bits for the LTSSM in its reference manual, others like i.MX6 uses 6 bits. However, the LTSSM states really have 5 bits, so we can safely use 5 bits (which corresponds to the 0x1f mask) for all the PCIe Designware cores.

Signed-off-by Fabio Estevam <[email protected]>

---
Changes since v2:
- Use LTSSM_STATE_MASK with value 0x1f for all the drivers (Lucas)
- Use lowercase in pcie-designware.h (Lucas)

 drivers/pci/host/pci-keystone-dw.c |  1 -
 drivers/pci/host/pci-layerscape.c  |  1 -
 drivers/pci/host/pcie-designware.h | 34 ++++++++++++++++++++++++++++++++++
 drivers/pci/host/pcie-spear13xx.c  | 33 ---------------------------------
 4 files changed, 34 insertions(+), 35 deletions(-)
drivers/pci/host/pci-keystone-dw.c +0 -1
index 0146b41..76edf92 100644
@@ -25,7 +25,6 @@
 
 /* Application register defines */
 #define LTSSM_EN_VAL		        1
-#define LTSSM_STATE_MASK		0x1f
 #define LTSSM_STATE_L0			0x11
 #define DBI_CS2_EN_VAL			0x20
 #define OB_XLAT_EN_VAL		        2
drivers/pci/host/pci-layerscape.c +0 -1
index 495a7c3..f68b551 100644
@@ -28,7 +28,6 @@
 /* PEX1/2 Misc Ports Status Register */
 #define SCFG_PEXMSCPORTSR(pex_idx)	(0x94 + (pex_idx) * 4)
 #define LTSSM_STATE_SHIFT	20
-#define LTSSM_STATE_MASK	0x3f
 #define LTSSM_PCIE_L0		0x11 /* L0 state */
 
 /* PEX Internal Configuration Registers */
drivers/pci/host/pcie-designware.h +34 -0
index e7b3279..95846dd 100644
@@ -22,6 +22,40 @@
 #define MAX_MSI_IRQS			32
 #define MAX_MSI_CTRLS			(MAX_MSI_IRQS / 32)
 
+#define LTSSM_STATE_DETECT_QUIET	0x00
+#define LTSSM_STATE_DETECT_ACT		0x01
+#define LTSSM_STATE_POLL_ACTIVE		0x02
+#define LTSSM_STATE_POLL_COMPLIANCE	0x03
+#define LTSSM_STATE_POLL_CONFIG		0x04
+#define LTSSM_STATE_PRE_DETECT_QUIET	0x05
+#define LTSSM_STATE_DETECT_WAIT		0x06
+#define LTSSM_STATE_CFG_LINKWD_START	0x07
+#define LTSSM_STATE_CFG_LINKWD_ACEPT	0x08
+#define LTSSM_STATE_CFG_LANENUM_WAIT	0x09
+#define LTSSM_STATE_CFG_LANENUM_ACEPT	0x0a
+#define LTSSM_STATE_CFG_COMPLETE	0x0b
+#define LTSSM_STATE_CFG_IDLE		0x0c
+#define LTSSM_STATE_RCVRY_LOCK		0x0d
+#define LTSSM_STATE_RCVRY_SPEED		0x0e
+#define LTSSM_STATE_RCVRY_RCVRCFG	0x0f
+#define LTSSM_STATE_RCVRY_IDLE		0x10
+#define LTSSM_STATE_L0			0x11
+#define LTSSM_STATE_L0S			0x12
+#define LTSSM_STATE_L123_SEND_EIDLE	0x13
+#define LTSSM_STATE_L1_IDLE		0x14
+#define LTSSM_STATE_L2_IDLE		0x15
+#define LTSSM_STATE_L2_WAKE		0x16
+#define LTSSM_STATE_DISABLED_ENTRY	0x17
+#define LTSSM_STATE_DISABLED_IDLE	0x18
+#define LTSSM_STATE_DISABLED		0x19
+#define LTSSM_STATE_LPBK_ENTRY		0x1a
+#define LTSSM_STATE_LPBK_ACTIVE		0x1b
+#define LTSSM_STATE_LPBK_EXIT		0x1c
+#define LTSSM_STATE_LPBK_EXIT_TIMEOUT	0x1d
+#define LTSSM_STATE_HOT_RESET_ENTRY	0x1e
+#define LTSSM_STATE_HOT_RESET		0x1f
+#define LTSSM_STATE_MASK		0x1f
+
 struct pcie_port {
 	struct device		*dev;
 	u8			root_bus_nr;
drivers/pci/host/pcie-spear13xx.c +0 -33
index b95b756..8f0a1a2 100644
@@ -84,39 +84,6 @@ struct pcie_app_reg {
 #define APPS_PM_XMT_PME_ID			5
 
 /* CR3 ID */
-#define XMLH_LTSSM_STATE_DETECT_QUIET		0x00
-#define XMLH_LTSSM_STATE_DETECT_ACT		0x01
-#define XMLH_LTSSM_STATE_POLL_ACTIVE		0x02
-#define XMLH_LTSSM_STATE_POLL_COMPLIANCE	0x03
-#define XMLH_LTSSM_STATE_POLL_CONFIG		0x04
-#define XMLH_LTSSM_STATE_PRE_DETECT_QUIET	0x05
-#define XMLH_LTSSM_STATE_DETECT_WAIT		0x06
-#define XMLH_LTSSM_STATE_CFG_LINKWD_START	0x07
-#define XMLH_LTSSM_STATE_CFG_LINKWD_ACEPT	0x08
-#define XMLH_LTSSM_STATE_CFG_LANENUM_WAIT	0x09
-#define XMLH_LTSSM_STATE_CFG_LANENUM_ACEPT	0x0A
-#define XMLH_LTSSM_STATE_CFG_COMPLETE		0x0B
-#define XMLH_LTSSM_STATE_CFG_IDLE		0x0C
-#define XMLH_LTSSM_STATE_RCVRY_LOCK		0x0D
-#define XMLH_LTSSM_STATE_RCVRY_SPEED		0x0E
-#define XMLH_LTSSM_STATE_RCVRY_RCVRCFG		0x0F
-#define XMLH_LTSSM_STATE_RCVRY_IDLE		0x10
-#define XMLH_LTSSM_STATE_L0			0x11
-#define XMLH_LTSSM_STATE_L0S			0x12
-#define XMLH_LTSSM_STATE_L123_SEND_EIDLE	0x13
-#define XMLH_LTSSM_STATE_L1_IDLE		0x14
-#define XMLH_LTSSM_STATE_L2_IDLE		0x15
-#define XMLH_LTSSM_STATE_L2_WAKE		0x16
-#define XMLH_LTSSM_STATE_DISABLED_ENTRY		0x17
-#define XMLH_LTSSM_STATE_DISABLED_IDLE		0x18
-#define XMLH_LTSSM_STATE_DISABLED		0x19
-#define XMLH_LTSSM_STATE_LPBK_ENTRY		0x1A
-#define XMLH_LTSSM_STATE_LPBK_ACTIVE		0x1B
-#define XMLH_LTSSM_STATE_LPBK_EXIT		0x1C
-#define XMLH_LTSSM_STATE_LPBK_EXIT_TIMEOUT	0x1D
-#define XMLH_LTSSM_STATE_HOT_RESET_ENTRY	0x1E
-#define XMLH_LTSSM_STATE_HOT_RESET		0x1F
-#define XMLH_LTSSM_STATE_MASK			0x3F
 #define XMLH_LINK_UP				(1 << 6)
 
 /* CR4 ID */
Signature · 1 line
1.9.1
author reviewer
#1 lore raw

PATCH v3 2/3 PCI: imx6: Use define instead of hard coded value

From: Fabio Estevam <[email protected]>

Use LTSSM_STATE_RCVRY_LOCK define instead of hard coded value in order to improve the code readability.

Signed-off-by Fabio Estevam <[email protected]>
Reviewed-by Lucas Stach <[email protected]>

---
Changes since v2:
- Use . instead of ; in the commit log

 drivers/pci/host/pci-imx6.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/pci/host/pci-imx6.c +1 -1
index 6f43086..4e7b577 100644
@@ -508,7 +508,7 @@ static int imx6_pcie_link_up(struct pcie_port *pp)
 	if (rx_valid & PCIE_PHY_RX_ASIC_OUT_VALID)
 		return 0;
 
-	if ((debug_r0 & PCIE_PHY_DEBUG_R0_LTSSM_MASK) != 0x0d)
+	if ((debug_r0 & PCIE_PHY_DEBUG_R0_LTSSM_MASK) != LTSSM_STATE_RCVRY_LOCK)
 		return 0;
 
 	dev_err(pp->dev, "transition to gen2 is stuck, reset PHY!\n");
Signature · 1 line
1.9.1
author reviewer
#2 lore raw

PATCH v3 3/3 PCI: imx6: Use the common LTSSM state mask

In reply to Fabio Estevam

From: Fabio Estevam <[email protected]>

Use the common LTSSM_STATE_MASK instead of a local definition.

Signed-off-by Fabio Estevam <[email protected]>

---
Changes since v2:
- Newly introduced in this version.

 drivers/pci/host/pci-imx6.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)
drivers/pci/host/pci-imx6.c +1 -2
index 4e7b577..4c788d27 100644
@@ -55,7 +55,6 @@ struct imx6_pcie {
 #define PCIE_PL_PFLR_LINK_STATE_MASK		(0x3f << 16)
 #define PCIE_PL_PFLR_FORCE_LINK			(1 << 15)
 #define PCIE_PHY_DEBUG_R0 (PL_OFFSET + 0x28)
-#define PCIE_PHY_DEBUG_R0_LTSSM_MASK		(0x3f << 0)
 #define PCIE_PHY_DEBUG_R1 (PL_OFFSET + 0x2c)
 #define PCIE_PHY_DEBUG_R1_XMLH_LINK_IN_TRAINING	(1 << 29)
 #define PCIE_PHY_DEBUG_R1_XMLH_LINK_UP		(1 << 4)

@@ -508,7 +507,7 @@ static int imx6_pcie_link_up(struct pcie_port *pp)
 	if (rx_valid & PCIE_PHY_RX_ASIC_OUT_VALID)
 		return 0;
 
-	if ((debug_r0 & PCIE_PHY_DEBUG_R0_LTSSM_MASK) != LTSSM_STATE_RCVRY_LOCK)
+	if ((debug_r0 & LTSSM_STATE_MASK) != LTSSM_STATE_RCVRY_LOCK)
 		return 0;
 
 	dev_err(pp->dev, "transition to gen2 is stuck, reset PHY!\n");
Signature · 1 line
1.9.1
Reviewed-by on v3 3/3
#3 lore raw

Re: [PATCH v3 3/3] PCI: imx6: Use the common LTSSM state mask

Am Montag, den 12.10.2015, 12:46 -0300 schrieb Fabio Estevam:

Quoted 5 lines

From: Fabio Estevam <[email protected]>

Use the common LTSSM_STATE_MASK instead of a local definition.

Signed-off-by Fabio Estevam <[email protected]>
Reviewed-by Lucas Stach <[email protected]>
Quoted 28 lines

---
Changes since v2:
- Newly introduced in this version.

 drivers/pci/host/pci-imx6.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)
drivers/pci/host/pci-imx6.c +1 -2
index 4e7b577..4c788d27 100644
@@ -55,7 +55,6 @@ struct imx6_pcie {
 #define PCIE_PL_PFLR_LINK_STATE_MASK		(0x3f << 16)
 #define PCIE_PL_PFLR_FORCE_LINK			(1 << 15)
 #define PCIE_PHY_DEBUG_R0 (PL_OFFSET + 0x28)
-#define PCIE_PHY_DEBUG_R0_LTSSM_MASK		(0x3f << 0)
 #define PCIE_PHY_DEBUG_R1 (PL_OFFSET + 0x2c)
 #define PCIE_PHY_DEBUG_R1_XMLH_LINK_IN_TRAINING	(1 << 29)
 #define PCIE_PHY_DEBUG_R1_XMLH_LINK_UP		(1 << 4)

@@ -508,7 +507,7 @@ static int imx6_pcie_link_up(struct pcie_port *pp)
 	if (rx_valid & PCIE_PHY_RX_ASIC_OUT_VALID)
 		return 0;
 
-	if ((debug_r0 & PCIE_PHY_DEBUG_R0_LTSSM_MASK) != LTSSM_STATE_RCVRY_LOCK)
+	if ((debug_r0 & LTSSM_STATE_MASK) != LTSSM_STATE_RCVRY_LOCK)
 		return 0;
 
 	dev_err(pp->dev, "transition to gen2 is stuck, reset PHY!\n");
Signature · 2 lines
Pengutronix e.K.             | Lucas Stach                 |
Industrial Linux Solutions   | http://www.pengutronix.de/  |
Reviewed-by on v3 1/3
#4 lore raw
In reply to Fabio Estevam

Am Montag, den 12.10.2015, 12:46 -0300 schrieb Fabio Estevam:

Quoted 8 lines

From: Fabio Estevam <[email protected]>

Move LTSSM state definitions to common pcie-designware.h so that other drivers can make use of them.

Also, LTSSM states only use 5 bits so use 0x1f as its mask, so that we have a common LTSSM mask accross all PCIe designware drivers.

Quoted 6 lines

Keystone uses 5 bits for the LTSSM in its reference manual, others like i.MX6 uses 6 bits. However, the LTSSM states really have 5 bits, so we can safely use 5 bits (which corresponds to the 0x1f mask) for all the PCIe Designware cores.

Signed-off-by Fabio Estevam <[email protected]>
Reviewed-by Lucas Stach <[email protected]>
Quoted 124 lines

---
Changes since v2:
- Use LTSSM_STATE_MASK with value 0x1f for all the drivers (Lucas)
- Use lowercase in pcie-designware.h (Lucas)

 drivers/pci/host/pci-keystone-dw.c |  1 -
 drivers/pci/host/pci-layerscape.c  |  1 -
 drivers/pci/host/pcie-designware.h | 34 ++++++++++++++++++++++++++++++++++
 drivers/pci/host/pcie-spear13xx.c  | 33 ---------------------------------
 4 files changed, 34 insertions(+), 35 deletions(-)
drivers/pci/host/pci-keystone-dw.c +0 -1
index 0146b41..76edf92 100644
@@ -25,7 +25,6 @@
 
 /* Application register defines */
 #define LTSSM_EN_VAL		        1
-#define LTSSM_STATE_MASK		0x1f
 #define LTSSM_STATE_L0			0x11
 #define DBI_CS2_EN_VAL			0x20
 #define OB_XLAT_EN_VAL		        2
drivers/pci/host/pci-layerscape.c +0 -1
index 495a7c3..f68b551 100644
@@ -28,7 +28,6 @@
 /* PEX1/2 Misc Ports Status Register */
 #define SCFG_PEXMSCPORTSR(pex_idx)	(0x94 + (pex_idx) * 4)
 #define LTSSM_STATE_SHIFT	20
-#define LTSSM_STATE_MASK	0x3f
 #define LTSSM_PCIE_L0		0x11 /* L0 state */
 
 /* PEX Internal Configuration Registers */
drivers/pci/host/pcie-designware.h +34 -0
index e7b3279..95846dd 100644
@@ -22,6 +22,40 @@
 #define MAX_MSI_IRQS			32
 #define MAX_MSI_CTRLS			(MAX_MSI_IRQS / 32)
 
+#define LTSSM_STATE_DETECT_QUIET	0x00
+#define LTSSM_STATE_DETECT_ACT		0x01
+#define LTSSM_STATE_POLL_ACTIVE		0x02
+#define LTSSM_STATE_POLL_COMPLIANCE	0x03
+#define LTSSM_STATE_POLL_CONFIG		0x04
+#define LTSSM_STATE_PRE_DETECT_QUIET	0x05
+#define LTSSM_STATE_DETECT_WAIT		0x06
+#define LTSSM_STATE_CFG_LINKWD_START	0x07
+#define LTSSM_STATE_CFG_LINKWD_ACEPT	0x08
+#define LTSSM_STATE_CFG_LANENUM_WAIT	0x09
+#define LTSSM_STATE_CFG_LANENUM_ACEPT	0x0a
+#define LTSSM_STATE_CFG_COMPLETE	0x0b
+#define LTSSM_STATE_CFG_IDLE		0x0c
+#define LTSSM_STATE_RCVRY_LOCK		0x0d
+#define LTSSM_STATE_RCVRY_SPEED		0x0e
+#define LTSSM_STATE_RCVRY_RCVRCFG	0x0f
+#define LTSSM_STATE_RCVRY_IDLE		0x10
+#define LTSSM_STATE_L0			0x11
+#define LTSSM_STATE_L0S			0x12
+#define LTSSM_STATE_L123_SEND_EIDLE	0x13
+#define LTSSM_STATE_L1_IDLE		0x14
+#define LTSSM_STATE_L2_IDLE		0x15
+#define LTSSM_STATE_L2_WAKE		0x16
+#define LTSSM_STATE_DISABLED_ENTRY	0x17
+#define LTSSM_STATE_DISABLED_IDLE	0x18
+#define LTSSM_STATE_DISABLED		0x19
+#define LTSSM_STATE_LPBK_ENTRY		0x1a
+#define LTSSM_STATE_LPBK_ACTIVE		0x1b
+#define LTSSM_STATE_LPBK_EXIT		0x1c
+#define LTSSM_STATE_LPBK_EXIT_TIMEOUT	0x1d
+#define LTSSM_STATE_HOT_RESET_ENTRY	0x1e
+#define LTSSM_STATE_HOT_RESET		0x1f
+#define LTSSM_STATE_MASK		0x1f
+
 struct pcie_port {
 	struct device		*dev;
 	u8			root_bus_nr;
drivers/pci/host/pcie-spear13xx.c +0 -33
index b95b756..8f0a1a2 100644
@@ -84,39 +84,6 @@ struct pcie_app_reg {
 #define APPS_PM_XMT_PME_ID			5
 
 /* CR3 ID */
-#define XMLH_LTSSM_STATE_DETECT_QUIET		0x00
-#define XMLH_LTSSM_STATE_DETECT_ACT		0x01
-#define XMLH_LTSSM_STATE_POLL_ACTIVE		0x02
-#define XMLH_LTSSM_STATE_POLL_COMPLIANCE	0x03
-#define XMLH_LTSSM_STATE_POLL_CONFIG		0x04
-#define XMLH_LTSSM_STATE_PRE_DETECT_QUIET	0x05
-#define XMLH_LTSSM_STATE_DETECT_WAIT		0x06
-#define XMLH_LTSSM_STATE_CFG_LINKWD_START	0x07
-#define XMLH_LTSSM_STATE_CFG_LINKWD_ACEPT	0x08
-#define XMLH_LTSSM_STATE_CFG_LANENUM_WAIT	0x09
-#define XMLH_LTSSM_STATE_CFG_LANENUM_ACEPT	0x0A
-#define XMLH_LTSSM_STATE_CFG_COMPLETE		0x0B
-#define XMLH_LTSSM_STATE_CFG_IDLE		0x0C
-#define XMLH_LTSSM_STATE_RCVRY_LOCK		0x0D
-#define XMLH_LTSSM_STATE_RCVRY_SPEED		0x0E
-#define XMLH_LTSSM_STATE_RCVRY_RCVRCFG		0x0F
-#define XMLH_LTSSM_STATE_RCVRY_IDLE		0x10
-#define XMLH_LTSSM_STATE_L0			0x11
-#define XMLH_LTSSM_STATE_L0S			0x12
-#define XMLH_LTSSM_STATE_L123_SEND_EIDLE	0x13
-#define XMLH_LTSSM_STATE_L1_IDLE		0x14
-#define XMLH_LTSSM_STATE_L2_IDLE		0x15
-#define XMLH_LTSSM_STATE_L2_WAKE		0x16
-#define XMLH_LTSSM_STATE_DISABLED_ENTRY		0x17
-#define XMLH_LTSSM_STATE_DISABLED_IDLE		0x18
-#define XMLH_LTSSM_STATE_DISABLED		0x19
-#define XMLH_LTSSM_STATE_LPBK_ENTRY		0x1A
-#define XMLH_LTSSM_STATE_LPBK_ACTIVE		0x1B
-#define XMLH_LTSSM_STATE_LPBK_EXIT		0x1C
-#define XMLH_LTSSM_STATE_LPBK_EXIT_TIMEOUT	0x1D
-#define XMLH_LTSSM_STATE_HOT_RESET_ENTRY	0x1E
-#define XMLH_LTSSM_STATE_HOT_RESET		0x1F
-#define XMLH_LTSSM_STATE_MASK			0x3F
 #define XMLH_LINK_UP				(1 << 6)
 
 /* CR4 ID */
Signature · 2 lines
Pengutronix e.K.             | Lucas Stach                 |
Industrial Linux Solutions   | http://www.pengutronix.de/  |
#5 lore raw
In reply to Fabio Estevam

Hi Fabio,

Quoted 5 lines · Fabio Estevam

From: Fabio Estevam <[email protected]>

Move LTSSM state definitions to common pcie-designware.h so that other drivers can make use of them.

Quoted 7 lines

Also, LTSSM states only use 5 bits so use 0x1f as its mask, so that we have a common LTSSM mask accross all PCIe designware drivers.

Keystone uses 5 bits for the LTSSM in its reference manual, others like i.MX6 uses 6 bits. However, the LTSSM states really have 5 bits, so we can safely use 5 bits (which corresponds to the 0x1f mask) for all the PCIe Designware cores.

Thanks for cleaning this up! I think if we split this up a little bit, the interesting parts will be more obvious. For instance, as far as I can tell, none of the spear13xx #defines are used at all, so removing them could be done ina separate patch. And I think it would be good to pull all the LTSSM_STATE_MASK-related changes into a single patch so it's obvious what's happening.

I'll post the patches I propose as a v4 series so you can see what you think.

Bjorn

Quoted 132 lines
Signed-off-by Fabio Estevam <[email protected]>

---
Changes since v2:
- Use LTSSM_STATE_MASK with value 0x1f for all the drivers (Lucas)
- Use lowercase in pcie-designware.h (Lucas)

 drivers/pci/host/pci-keystone-dw.c |  1 -
 drivers/pci/host/pci-layerscape.c  |  1 -
 drivers/pci/host/pcie-designware.h | 34 ++++++++++++++++++++++++++++++++++
 drivers/pci/host/pcie-spear13xx.c  | 33 ---------------------------------
 4 files changed, 34 insertions(+), 35 deletions(-)
drivers/pci/host/pci-keystone-dw.c +0 -1
index 0146b41..76edf92 100644
@@ -25,7 +25,6 @@
 
 /* Application register defines */
 #define LTSSM_EN_VAL		        1
-#define LTSSM_STATE_MASK		0x1f
 #define LTSSM_STATE_L0			0x11
 #define DBI_CS2_EN_VAL			0x20
 #define OB_XLAT_EN_VAL		        2
drivers/pci/host/pci-layerscape.c +0 -1
index 495a7c3..f68b551 100644
@@ -28,7 +28,6 @@
 /* PEX1/2 Misc Ports Status Register */
 #define SCFG_PEXMSCPORTSR(pex_idx)	(0x94 + (pex_idx) * 4)
 #define LTSSM_STATE_SHIFT	20
-#define LTSSM_STATE_MASK	0x3f
 #define LTSSM_PCIE_L0		0x11 /* L0 state */
 
 /* PEX Internal Configuration Registers */
drivers/pci/host/pcie-designware.h +34 -0
index e7b3279..95846dd 100644
@@ -22,6 +22,40 @@
 #define MAX_MSI_IRQS			32
 #define MAX_MSI_CTRLS			(MAX_MSI_IRQS / 32)
 
+#define LTSSM_STATE_DETECT_QUIET	0x00
+#define LTSSM_STATE_DETECT_ACT		0x01
+#define LTSSM_STATE_POLL_ACTIVE		0x02
+#define LTSSM_STATE_POLL_COMPLIANCE	0x03
+#define LTSSM_STATE_POLL_CONFIG		0x04
+#define LTSSM_STATE_PRE_DETECT_QUIET	0x05
+#define LTSSM_STATE_DETECT_WAIT		0x06
+#define LTSSM_STATE_CFG_LINKWD_START	0x07
+#define LTSSM_STATE_CFG_LINKWD_ACEPT	0x08
+#define LTSSM_STATE_CFG_LANENUM_WAIT	0x09
+#define LTSSM_STATE_CFG_LANENUM_ACEPT	0x0a
+#define LTSSM_STATE_CFG_COMPLETE	0x0b
+#define LTSSM_STATE_CFG_IDLE		0x0c
+#define LTSSM_STATE_RCVRY_LOCK		0x0d
+#define LTSSM_STATE_RCVRY_SPEED		0x0e
+#define LTSSM_STATE_RCVRY_RCVRCFG	0x0f
+#define LTSSM_STATE_RCVRY_IDLE		0x10
+#define LTSSM_STATE_L0			0x11
+#define LTSSM_STATE_L0S			0x12
+#define LTSSM_STATE_L123_SEND_EIDLE	0x13
+#define LTSSM_STATE_L1_IDLE		0x14
+#define LTSSM_STATE_L2_IDLE		0x15
+#define LTSSM_STATE_L2_WAKE		0x16
+#define LTSSM_STATE_DISABLED_ENTRY	0x17
+#define LTSSM_STATE_DISABLED_IDLE	0x18
+#define LTSSM_STATE_DISABLED		0x19
+#define LTSSM_STATE_LPBK_ENTRY		0x1a
+#define LTSSM_STATE_LPBK_ACTIVE		0x1b
+#define LTSSM_STATE_LPBK_EXIT		0x1c
+#define LTSSM_STATE_LPBK_EXIT_TIMEOUT	0x1d
+#define LTSSM_STATE_HOT_RESET_ENTRY	0x1e
+#define LTSSM_STATE_HOT_RESET		0x1f
+#define LTSSM_STATE_MASK		0x1f
+
 struct pcie_port {
 	struct device		*dev;
 	u8			root_bus_nr;
drivers/pci/host/pcie-spear13xx.c +0 -33
index b95b756..8f0a1a2 100644
@@ -84,39 +84,6 @@ struct pcie_app_reg {
 #define APPS_PM_XMT_PME_ID			5
 
 /* CR3 ID */
-#define XMLH_LTSSM_STATE_DETECT_QUIET		0x00
-#define XMLH_LTSSM_STATE_DETECT_ACT		0x01
-#define XMLH_LTSSM_STATE_POLL_ACTIVE		0x02
-#define XMLH_LTSSM_STATE_POLL_COMPLIANCE	0x03
-#define XMLH_LTSSM_STATE_POLL_CONFIG		0x04
-#define XMLH_LTSSM_STATE_PRE_DETECT_QUIET	0x05
-#define XMLH_LTSSM_STATE_DETECT_WAIT		0x06
-#define XMLH_LTSSM_STATE_CFG_LINKWD_START	0x07
-#define XMLH_LTSSM_STATE_CFG_LINKWD_ACEPT	0x08
-#define XMLH_LTSSM_STATE_CFG_LANENUM_WAIT	0x09
-#define XMLH_LTSSM_STATE_CFG_LANENUM_ACEPT	0x0A
-#define XMLH_LTSSM_STATE_CFG_COMPLETE		0x0B
-#define XMLH_LTSSM_STATE_CFG_IDLE		0x0C
-#define XMLH_LTSSM_STATE_RCVRY_LOCK		0x0D
-#define XMLH_LTSSM_STATE_RCVRY_SPEED		0x0E
-#define XMLH_LTSSM_STATE_RCVRY_RCVRCFG		0x0F
-#define XMLH_LTSSM_STATE_RCVRY_IDLE		0x10
-#define XMLH_LTSSM_STATE_L0			0x11
-#define XMLH_LTSSM_STATE_L0S			0x12
-#define XMLH_LTSSM_STATE_L123_SEND_EIDLE	0x13
-#define XMLH_LTSSM_STATE_L1_IDLE		0x14
-#define XMLH_LTSSM_STATE_L2_IDLE		0x15
-#define XMLH_LTSSM_STATE_L2_WAKE		0x16
-#define XMLH_LTSSM_STATE_DISABLED_ENTRY		0x17
-#define XMLH_LTSSM_STATE_DISABLED_IDLE		0x18
-#define XMLH_LTSSM_STATE_DISABLED		0x19
-#define XMLH_LTSSM_STATE_LPBK_ENTRY		0x1A
-#define XMLH_LTSSM_STATE_LPBK_ACTIVE		0x1B
-#define XMLH_LTSSM_STATE_LPBK_EXIT		0x1C
-#define XMLH_LTSSM_STATE_LPBK_EXIT_TIMEOUT	0x1D
-#define XMLH_LTSSM_STATE_HOT_RESET_ENTRY	0x1E
-#define XMLH_LTSSM_STATE_HOT_RESET		0x1F
-#define XMLH_LTSSM_STATE_MASK			0x3F
 #define XMLH_LINK_UP				(1 << 6)
 
 /* CR4 ID */
Signature · 6 lines
1.9.1

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