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target-xtensa: two new instructions

PATCH New Max Filippov 1 participant 3 messages Oct 14, 2015

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Max Filippov

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#0 lore raw

cover target-xtensa: two new instructions

Hi,

this series adds two new xtensa instructions:
- s32nb is a new core instruction;
- depbits is enabled by dedicated option.

Max Filippov (2):
target-xtensa: implement depbits instruction
target-xtensa: implement S32NB

 target-xtensa/cpu.h          |  1 +
 target-xtensa/overlay_tool.h |  5 +++++
 target-xtensa/translate.c    | 31 +++++++++++++++++++++++++++++++
 3 files changed, 37 insertions(+)
Signature · 1 line
1.8.1.4
author
#1 lore raw

PATCH 1/2 target-xtensa: implement depbits instruction

This option provides an instruction for depositing a bit field from the least significant position of one register to an arbitrary position in another register.

Signed-off-by Max Filippov <[email protected]>
---
 target-xtensa/cpu.h          |  1 +
 target-xtensa/overlay_tool.h |  5 +++++
 target-xtensa/translate.c    | 20 ++++++++++++++++++++
 3 files changed, 26 insertions(+)
target-xtensa/cpu.h +1 -0
index 96bfc82..a45cb39 100644
@@ -65,6 +65,7 @@ enum {
     XTENSA_OPTION_MP_SYNCHRO,
     XTENSA_OPTION_CONDITIONAL_STORE,
     XTENSA_OPTION_ATOMCTL,
+    XTENSA_OPTION_DEPBITS,
 
     /* Interrupts and exceptions */
     XTENSA_OPTION_EXCEPTION,
target-xtensa/overlay_tool.h +5 -0
index eda03aa..e8a7fda 100644
@@ -30,6 +30,10 @@
     { .targno = (no), .type = (typ), .group = (grp), .size = (sz) },
 #define XTREG_END { .targno = -1 },
 
+#ifndef XCHAL_HAVE_DEPBITS
+#define XCHAL_HAVE_DEPBITS 0
+#endif
+
 #ifndef XCHAL_HAVE_DIV32
 #define XCHAL_HAVE_DIV32 0
 #endif

@@ -69,6 +73,7 @@
     XCHAL_OPTION(XCHAL_HAVE_S32C1I, XTENSA_OPTION_CONDITIONAL_STORE) | \
     XCHAL_OPTION(XCHAL_HAVE_S32C1I && XCHAL_HW_MIN_VERSION >= 230000, \
         XTENSA_OPTION_ATOMCTL) | \
+    XCHAL_OPTION(XCHAL_HAVE_DEPBITS, XTENSA_OPTION_DEPBITS) | \
     /* Interrupts and exceptions */ \
     XCHAL_OPTION(XCHAL_HAVE_EXCEPTIONS, XTENSA_OPTION_EXCEPTION) | \
     XCHAL_OPTION(XCHAL_HAVE_VECBASE, XTENSA_OPTION_RELOCATABLE_VECTOR) | \
target-xtensa/translate.c +20 -0
index f2118c2..cd2148e 100644
@@ -1970,6 +1970,16 @@ static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc)
             break;
 
         case 10: /*FP0*/
+            /*DEPBITS*/
+            if (option_enabled(dc, XTENSA_OPTION_DEPBITS)) {
+                if (!gen_window_check2(dc, RRR_S, RRR_T)) {
+                    break;
+                }
+                tcg_gen_deposit_i32(cpu_R[RRR_T], cpu_R[RRR_T], cpu_R[RRR_S],
+                                    OP2, RRR_R + 1);
+                break;
+            }
+
             HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR);
             switch (OP2) {
             case 0: /*ADD.Sf*/

@@ -2104,6 +2114,16 @@ static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc)
             break;
 
         case 11: /*FP1*/
+            /*DEPBITS*/
+            if (option_enabled(dc, XTENSA_OPTION_DEPBITS)) {
+                if (!gen_window_check2(dc, RRR_S, RRR_T)) {
+                    break;
+                }
+                tcg_gen_deposit_i32(cpu_R[RRR_T], cpu_R[RRR_T], cpu_R[RRR_S],
+                                    OP2 + 16, RRR_R + 1);
+                break;
+            }
+
             HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR);
 
 #define gen_compare(rel, br, a, b) \
Signature · 1 line
1.8.1.4
author
#2 lore raw

PATCH 2/2 target-xtensa: implement S32NB

In reply to Max Filippov

S32NB provides the same functionality as S32I with two exceptions. First, when its operation leaves the processor, the external transaction is marked Non-Bufferable. Second, it may not be used to write to Instruction RAM.
In QEMU S32NB is equivalent to S32I.

Signed-off-by Max Filippov <[email protected]>
---
 target-xtensa/translate.c | 11 +++++++++++
 1 file changed, 11 insertions(+)
target-xtensa/translate.c +11 -0
index cd2148e..9b6033d 100644
@@ -1963,6 +1963,17 @@ static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc)
                 }
                 break;
 
+            case 5: /*S32N*/
+                if (gen_window_check2(dc, RRI4_S, RRI4_T)) {
+                    TCGv_i32 addr = tcg_temp_new_i32();
+
+                    tcg_gen_addi_i32(addr, cpu_R[RRI4_S], RRI4_IMM4 << 2);
+                    gen_load_store_alignment(dc, 2, addr, false);
+                    tcg_gen_qemu_st32(cpu_R[RRI4_T], addr, dc->cring);
+                    tcg_temp_free(addr);
+                }
+                break;
+
             default:
                 RESERVED();
                 break;
Signature · 1 line
1.8.1.4