Patch "irqchip/atmel-aic5: Use per chip mask caches in mask/unmask()" has been added to the 4.1-stable tree

PATCH gregkh at linuxfoundation.org 1 participant 1 message Oct 17, 2015

Subsystems (3)

Stable branch Arm/Microchip (AT91) SoC support irqchip drivers

lore

Share & tools

lore

gregkh at linuxfoundation.org

author maintainer Applied

2015-10-17 22:04 UTC #0 lore raw

This is a note to let you know that I've just added the patch titled

irqchip/atmel-aic5: Use per chip mask caches in mask/unmask()

to the 4.1-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
irqchip-atmel-aic5-use-per-chip-mask-caches-in-mask-unmask.patch
and it can be found in the queue-4.1 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree, please let <[email protected]> know about it.

Quoted 1 line

From d32dc9aa10c739363c775baf4499416b2e0dc11f Mon Sep 17 00:00:00 2001

From: Ludovic Desroches <[email protected]>
Date: Mon, 21 Sep 2015 15:46:04 +0200
Subject: irqchip/atmel-aic5: Use per chip mask caches in mask/unmask()

From: Ludovic Desroches <[email protected]>

commit d32dc9aa10c739363c775baf4499416b2e0dc11f upstream.

When masking/unmasking interrupts, mask_cache is updated and used later for suspend/resume. Unfortunately, it always was the mask_cache associated with the first irq chip which was updated. So when performing resume, only irqs 0-31 could be enabled.

Fixes b1479ebb7720 ("irqchip: atmel-aic: Add atmel AIC/AIC5 drivers")

Signed-off-by Ludovic Desroches <[email protected]>

Cc <[email protected]>

Link http://lkml.kernel.org/r/1442843173-2390-1-git-send-email-ludovic.desroches at atmel.com

Signed-off-by Thomas Gleixner <[email protected]>

Signed-off-by Greg Kroah-Hartman <[email protected]>

---
 drivers/irqchip/irq-atmel-aic5.c |   24 ++++++++++++++++--------
 1 file changed, 16 insertions(+), 8 deletions(-)

drivers/irqchip/irq-atmel-aic5.c +16 -8

@@ -88,28 +88,36 @@ static void aic5_mask(struct irq_data *d
 {
 	struct irq_domain *domain = d->domain;
 	struct irq_domain_chip_generic *dgc = domain->gc;
-	struct irq_chip_generic *gc = dgc->gc[0];
+	struct irq_chip_generic *bgc = dgc->gc[0];
+	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
 
-	/* Disable interrupt on AIC5 */
-	irq_gc_lock(gc);
+	/*
+	 * Disable interrupt on AIC5. We always take the lock of the
+	 * first irq chip as all chips share the same registers.
+	 */
+	irq_gc_lock(bgc);
 	irq_reg_writel(gc, d->hwirq, AT91_AIC5_SSR);
 	irq_reg_writel(gc, 1, AT91_AIC5_IDCR);
 	gc->mask_cache &= ~d->mask;
-	irq_gc_unlock(gc);
+	irq_gc_unlock(bgc);
 }
 
 static void aic5_unmask(struct irq_data *d)
 {
 	struct irq_domain *domain = d->domain;
 	struct irq_domain_chip_generic *dgc = domain->gc;
-	struct irq_chip_generic *gc = dgc->gc[0];
+	struct irq_chip_generic *bgc = dgc->gc[0];
+	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
 
-	/* Enable interrupt on AIC5 */
-	irq_gc_lock(gc);
+	/*
+	 * Enable interrupt on AIC5. We always take the lock of the
+	 * first irq chip as all chips share the same registers.
+	 */
+	irq_gc_lock(bgc);
 	irq_reg_writel(gc, d->hwirq, AT91_AIC5_SSR);
 	irq_reg_writel(gc, 1, AT91_AIC5_IECR);
 	gc->mask_cache |= d->mask;
-	irq_gc_unlock(gc);
+	irq_gc_unlock(bgc);
 }
 
 static int aic5_retrigger(struct irq_data *d)

Patches currently in stable-queue which might be from ludovic.desroches at atmel.com are

queue-4.1/irqchip-atmel-aic5-use-per-chip-mask-caches-in-mask-unmask.patch