Patch "drm/i915: Flush pipecontrol post-sync writes" has been added to the 4.2-stable tree

This is a note to let you know that I've just added the patch titled

drm/i915: Flush pipecontrol post-sync writes

to the 4.2-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
drm-i915-flush-pipecontrol-post-sync-writes.patch
and it can be found in the queue-4.2 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree, please let <[email protected]> know about it.

From: Chris Wilson <[email protected]>
Date: Fri, 21 Aug 2015 16:08:41 +0100
Subject: drm/i915: Flush pipecontrol post-sync writes
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From: Chris Wilson <[email protected]>

commit 40a24488f5250d63341e74b9994159afc4589606 upstream.

In order to flush the results from in-batch pipecontrol writes (used for example in glQuery) before declaring the batch complete (and so declaring the query results coherent), we need to set the FlushEnable bit in our flushing pipecontrol. The FlushEnable bit "waits until all previous writes of immediate data from post-sync circles are complete before executing the next command".

I get GPU hangs on byt without flushing these writes (running ue4). piglit has examples where the flush is required for correct rendering.

---
 drivers/gpu/drm/i915/intel_lrc.c        |    1 +
 drivers/gpu/drm/i915/intel_ringbuffer.c |    2 ++
 2 files changed, 3 insertions(+)

@@ -1250,6 +1250,7 @@ static int gen8_emit_flush_render(struct
 	if (flush_domains) {
 		flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 		flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
+		flags |= PIPE_CONTROL_FLUSH_ENABLE;
 	}
 
 	if (invalidate_domains) {

@@ -342,6 +342,7 @@ gen7_render_ring_flush(struct intel_engi
 	if (flush_domains) {
 		flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 		flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
+		flags |= PIPE_CONTROL_FLUSH_ENABLE;
 	}
 	if (invalidate_domains) {
 		flags |= PIPE_CONTROL_TLB_INVALIDATE;

@@ -412,6 +413,7 @@ gen8_render_ring_flush(struct intel_engi
 	if (flush_domains) {
 		flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 		flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
+		flags |= PIPE_CONTROL_FLUSH_ENABLE;
 	}
 	if (invalidate_domains) {
 		flags |= PIPE_CONTROL_TLB_INVALIDATE;

Patches currently in stable-queue which might be from [email protected] are

queue-4.2/drm-i915-flush-pipecontrol-post-sync-writes.patch queue-4.2/drm-i915-deny-wrapping-an-userptr-into-a-framebuffer.patch