drm/i915: add WaIncreaseDefaultTLBEntries
Subsystems (2)
cover drm/i915: add WaIncreaseDefaultTLBEntries
From: Tim Gore <[email protected]>
These 3 patches introduce a performance workaround that can have significant impact (> 10%) on some OCL workloads. It is split into 3 patches as follows.
1) The first patch introduces a new function to collect together workarounds that are GT specific and apply globally across the GPU (as opposed to per ring or per context). This function is called at driver load and on resume (from suspend) and after a GPU reset, so it can host worarounds that are clobbered by these events. This new function was suggested by Mika Kuoppala.
2) The second patch adds WaIncreaseDefaultTLBEntries for gen8 GPU's to the above function.
3) Finally add WaIncreaseDefaultTLBEntries for gen9.
Tim Gore (3):
drm/i915: add function for GT related workarounds drm/i915/gen8: add WaIncreaseDefaultTLBEntries drm/i915/gen9: add WaIncreaseDefaultTLBEntries
drivers/gpu/drm/i915/i915_gem_gtt.c | 21 +++++++++++++++++++++ drivers/gpu/drm/i915/i915_reg.h | 7 +++++++ 2 files changed, 28 insertions(+)
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1.9.1 _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
PATCH 1/3 drm/i915: add function for GT related workarounds
From: Tim Gore <[email protected]>
Add a function that is a place for workarounds that are GT related but not required per ring. This function is called on driver load and also after a reset and on resume, so it is safe for workarounds that get clobbered in these situations.
--- drivers/gpu/drm/i915/i915_gem_gtt.c | 12 ++++++++++++ 1 file changed, 12 insertions(+)
drivers/gpu/drm/i915/i915_gem_gtt.c +12 -0
@@ -2132,6 +2132,16 @@ static void i915_address_space_init(struct i915_address_space *vm,list_add_tail (&vm->global_link, &dev_priv->vm_list); } +void gtt_write_workarounds (struct drm_device *dev) +{ +struct drm_i915_private *dev_priv = dev->dev_private; + +/* This function is for gtt related workarounds. This function is +* called on driver load and after a GPU reset, so you can place +* workarounds here even if they get overwritten by GPU reset. +*/ +} +int i915_ppgtt_init (struct drm_device *dev,struct i915_hw_ppgtt *ppgtt) {struct drm_i915_private *dev_priv = dev->dev_private;
@@ -2148,6 +2158,8 @@ int i915_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt)int i915_ppgtt_init_hw (struct drm_device *dev) { +gtt_write_workarounds (dev); +/* In the case of execlists, PPGTT is enabled by the context descriptor * and the PDPs are contained within the context itself. We don't * need to do anything here. */
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Re: [PATCH 1/3] drm/i915: add function for GT related workarounds
Quoted 18 lines · [email protected] writes:
From: Tim Gore <[email protected]>
Add a function that is a place for workarounds that are GT related but not required per ring. This function is called on driver load and also after a reset and on resume, so it is safe for workarounds that get clobbered in these situations.
Signed-off-by Tim Gore <[email protected]>--- drivers/gpu/drm/i915/i915_gem_gtt.c | 12 ++++++++++++ 1 file changed, 12 insertions(+)drivers/gpu/drm/i915/i915_gem_gtt.c +0
-0
drivers/gpu/drm/i915/i915_gem_gtt.c static void i915_address_space_init(struct i915_address_space *vm, · line 2136
Quoted 5 lines
drivers/gpu/drm/i915/i915_gem_gtt.c +2
-0@@ -2132,6 +2132,16 @@ static void i915_address_space_init(struct i915_address_space *vm,list_add_tail (&vm->global_link, &dev_priv->vm_list); } +void gtt_write_workarounds (struct drm_device *dev) +{
static void
This can be squashed with 2/3.
-Mika
Quoted 22 lines
drivers/gpu/drm/i915/i915_gem_gtt.c +10
-0+struct drm_i915_private *dev_priv = dev->dev_private; + +/* This function is for gtt related workarounds. This function is +* called on driver load and after a GPU reset, so you can place +* workarounds here even if they get overwritten by GPU reset. +*/ +} +int i915_ppgtt_init (struct drm_device *dev,struct i915_hw_ppgtt *ppgtt) {struct drm_i915_private *dev_priv = dev->dev_private;@@ -2148,6 +2158,8 @@ int i915_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt)int i915_ppgtt_init_hw (struct drm_device *dev) { +gtt_write_workarounds (dev); +/* In the case of execlists, PPGTT is enabled by the context descriptor * and the PDPs are contained within the context itself. We don't * need to do anything here. */ Signature · 1 line
1.9.1
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Re: [PATCH 1/3] drm/i915: add function for GT related workarounds
Tim Gore
Intel Corporation (UK) Ltd. - Co. Reg. #1134945 - Pipers Way, Swindon SN3 1RJ
Quoted 30 lines
-----Original Message-----
From: Mika Kuoppala [mailto:[email protected]]
Sent: Monday, January 25, 2016 2:39 PM
To: Gore, Tim; [email protected]
Cc: Gore, Tim; [email protected]
Subject: Re: [PATCH 1/3] drm/i915: add function for GT related workaroundsdrivers/gpu/drm/i915/i915_gem_gtt.c static void i915_address_space_init(struct
Quoted 18 lines · [email protected] writes:
From: Tim Gore <[email protected]>
Add a function that is a place for workarounds that are GT related but not required per ring. This function is called on driver load and also after a reset and on resume, so it is safe for workarounds that get clobbered in these situations.
Signed-off-by Tim Gore <[email protected]>--- drivers/gpu/drm/i915/i915_gem_gtt.c | 12 ++++++++++++ 1 file changed, 12 insertions(+)drivers/gpu/drm/i915/i915_gem_gtt.c +0
-0@@ -2132,6 +2132,16 @@ static void i915_address_space_init(struct
i915_address_space*vm,Quoted 2 lines
drivers/gpu/drm/i915/i915_gem_gtt.c +0
-0list_add_tail (&vm->global_link, &dev_priv->vm_list); }
Quoted 8 lines
drivers/gpu/drm/i915/i915_gem_gtt.c static void i915_address_space_init(struct · line 2134
Quoted 1 line
drivers/gpu/drm/i915/i915_gem_gtt.c +1
-0+void gtt_write_workarounds (struct drm_device *dev) {static void
This can be squashed with 2/3.
-Mika
Do you mean all squashed together, into a single patch?
Tim
Quoted 14 lines
Quoted 14 lines
drivers/gpu/drm/i915/i915_gem_gtt.c +9
-0+struct drm_i915_private *dev_priv = dev->dev_private; + +/* This function is for gtt related workarounds. This function is +* called on driver load and after a GPU reset, so you can place +* workarounds here even if they get overwritten by GPU reset. +*/ +} +int i915_ppgtt_init (struct drm_device *dev,struct i915_hw_ppgtt *ppgtt) { struct drm_i915_private *dev_priv = dev->dev_private; @@ -2148,6 +2158,8 @@ int i915_ppgtt_init(struct drm_device *dev, structi915_hw_ppgtt *ppgtt)
Quoted 9 lines
drivers/gpu/drm/i915/i915_gem_gtt.c int i915_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt)
Quoted 4 lines
int
i915_ppgtt_init_hw(struct drm_device *dev){drivers/gpu/drm/i915/i915_gem_gtt.c +2
-0+gtt_write_workarounds (dev); +/* In the case of execlists, PPGTT is enabled by the context descriptor
Quoted 4 lines
drivers/gpu/drm/i915/i915_gem_gtt.c +0
-1* and the PDPs are contained within the context itself. We don't * need to do anything here. */ --1.9.1
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Re: [PATCH 1/3] drm/i915: add function for GT related workarounds
Quoted 38 lines · Tim
Tim Gore
Intel Corporation (UK) Ltd. - Co. Reg. #1134945 - Pipers Way, Swindon SN3 1RJQuoted 32 lines
-----Original Message-----
From: Mika Kuoppala [mailto:[email protected]]
Sent: Monday, January 25, 2016 2:39 PM
To: Gore, Tim; [email protected]
Cc: Gore, Tim; [email protected]
Subject: Re: [PATCH 1/3] drm/i915: add function for GT related workaroundsdrivers/gpu/drm/i915/i915_gem_gtt.c static void i915_address_space_init(struct
Quoted 18 lines · [email protected] writes:
From: Tim Gore <[email protected]>
Add a function that is a place for workarounds that are GT related but not required per ring. This function is called on driver load and also after a reset and on resume, so it is safe for workarounds that get clobbered in these situations.
Signed-off-by Tim Gore <[email protected]>--- drivers/gpu/drm/i915/i915_gem_gtt.c | 12 ++++++++++++ 1 file changed, 12 insertions(+)drivers/gpu/drm/i915/i915_gem_gtt.c +0
-0@@ -2132,6 +2132,16 @@ static void i915_address_space_init(struct
i915_address_space*vm,Quoted 3 lines
drivers/gpu/drm/i915/i915_gem_gtt.c +1
-0list_add_tail (&vm->global_link, &dev_priv->vm_list); } +void gtt_write_workarounds (struct drm_device *dev) {
Quoted 7 lines
Quoted 6 lines
static void
This can be squashed with 2/3.
-Mika
Do you mean all squashed together, into a single patch?
I would. They are all setting the same register to a nominal value, for the same purpose.
u32 val;
/* Wa:bar,foo,baz */
val = 0;
if (is_bar(dev_priv))
val = 1; else if (is_foo(dev_priv)) val = 2; else if (is_baz(dev_priv)) val = 3; if (val) I915_WRITE(REG, val);
Would result in slightly less horrendous code.
-Chris
Signature · 5 lines
Chris Wilson, Intel Open Source Technology Centre _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [PATCH 1/3] drm/i915: add function for GT related workarounds
Quoted 41 lines · Chris Wilson
Quoted 40 lines · Tim
Tim Gore
Intel Corporation (UK) Ltd. - Co. Reg. #1134945 - Pipers Way, Swindon SN3 1RJQuoted 34 lines
-----Original Message-----
From: Mika Kuoppala [mailto:[email protected]]
Sent: Monday, January 25, 2016 2:39 PM
To: Gore, Tim; [email protected]
Cc: Gore, Tim; [email protected]
Subject: Re: [PATCH 1/3] drm/i915: add function for GT related workaroundsdrivers/gpu/drm/i915/i915_gem_gtt.c static void i915_address_space_init(struct
Quoted 18 lines · [email protected] writes:
From: Tim Gore <[email protected]>
Add a function that is a place for workarounds that are GT related but not required per ring. This function is called on driver load and also after a reset and on resume, so it is safe for workarounds that get clobbered in these situations.
Signed-off-by Tim Gore <[email protected]>--- drivers/gpu/drm/i915/i915_gem_gtt.c | 12 ++++++++++++ 1 file changed, 12 insertions(+)drivers/gpu/drm/i915/i915_gem_gtt.c +0
-0@@ -2132,6 +2132,16 @@ static void i915_address_space_init(struct
i915_address_space*vm,drivers/gpu/drm/i915/i915_gem_gtt.c static void i915_address_space_init(struct · line 2134
Quoted 3 lines
drivers/gpu/drm/i915/i915_gem_gtt.c +1
-0list_add_tail (&vm->global_link, &dev_priv->vm_list); } +void gtt_write_workarounds (struct drm_device *dev) {static void
Quoted 8 lines
Quoted 5 lines
Quoted 4 lines
This can be squashed with 2/3.
-Mika
Do you mean all squashed together, into a single patch?
I would. They are all setting the same register to a nominal value, for the same purpose.
Don't we normally split WA into individual patches or is this only for this WA?
regards
Arun
Quoted 14 lines
u32 val;
/* Wa:bar,foo,baz */
val = 0;
if (is_bar(dev_priv))val = 1; else if (is_foo(dev_priv)) val = 2; else if (is_baz(dev_priv)) val = 3; if (val) I915_WRITE(REG, val);
Quoted 3 lines
Would result in slightly less horrendous code.
-Chris
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Re: [PATCH 1/3] drm/i915: add function for GT related workarounds
Quoted 46 lines · Arun Siluvery
Quoted 45 lines · Chris Wilson
Quoted 44 lines · Tim
Tim Gore
Intel Corporation (UK) Ltd. - Co. Reg. #1134945 - Pipers Way, Swindon SN3 1RJQuoted 38 lines
-----Original Message-----
From: Mika Kuoppala [mailto:[email protected]]
Sent: Monday, January 25, 2016 2:39 PM
To: Gore, Tim; [email protected]
Cc: Gore, Tim; [email protected]
Subject: Re: [PATCH 1/3] drm/i915: add function for GT related workaroundsdrivers/gpu/drm/i915/i915_gem_gtt.c static void i915_address_space_init(struct
Quoted 18 lines · [email protected] writes:
From: Tim Gore <[email protected]>
Add a function that is a place for workarounds that are GT related but not required per ring. This function is called on driver load and also after a reset and on resume, so it is safe for workarounds that get clobbered in these situations.
Signed-off-by Tim Gore <[email protected]>--- drivers/gpu/drm/i915/i915_gem_gtt.c | 12 ++++++++++++ 1 file changed, 12 insertions(+)drivers/gpu/drm/i915/i915_gem_gtt.c +0
-0@@ -2132,6 +2132,16 @@ static void i915_address_space_init(struct
i915_address_space*vm,drivers/gpu/drm/i915/i915_gem_gtt.c static void i915_address_space_init(struct · line 2134
Quoted 3 lines
drivers/gpu/drm/i915/i915_gem_gtt.c +1
-0list_add_tail (&vm->global_link, &dev_priv->vm_list); } +void gtt_write_workarounds (struct drm_device *dev) {static void
This can be squashed with 2/3.
-Mika
Quoted 7 lines
Quoted 4 lines
Quoted 1 line
Do you mean all squashed together, into a single patch?
I would. They are all setting the same register to a nominal value, for the same purpose.
Don't we normally split WA into individual patches or is this only for this WA?
Is it not the same w/a applied to different generations? You either split it per device, so that a bisect + revert only affects one machine, or not all. Choose your poison.
-Chris
Signature · 5 lines
Chris Wilson, Intel Open Source Technology Centre _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [PATCH 1/3] drm/i915: add function for GT related workarounds
Quoted 52 lines · Chris Wilson
Quoted 51 lines · Arun Siluvery
Quoted 49 lines · Chris Wilson
Quoted 38 lines · Tim
Tim Gore
Intel Corporation (UK) Ltd. - Co. Reg. #1134945 - Pipers Way, Swindon SN3 1RJQuoted 32 lines
-----Original Message-----
From: Mika Kuoppala [mailto:[email protected]]
Sent: Monday, January 25, 2016 2:39 PM
To: Gore, Tim; [email protected]
Cc: Gore, Tim; [email protected]
Subject: Re: [PATCH 1/3] drm/i915: add function for GT related workaroundsdrivers/gpu/drm/i915/i915_gem_gtt.c static void i915_address_space_init(struct
Quoted 18 lines · [email protected] writes:
From: Tim Gore <[email protected]>
Add a function that is a place for workarounds that are GT related but not required per ring. This function is called on driver load and also after a reset and on resume, so it is safe for workarounds that get clobbered in these situations.
Signed-off-by Tim Gore <[email protected]>--- drivers/gpu/drm/i915/i915_gem_gtt.c | 12 ++++++++++++ 1 file changed, 12 insertions(+)drivers/gpu/drm/i915/i915_gem_gtt.c +0
-0@@ -2132,6 +2132,16 @@ static void i915_address_space_init(struct
i915_address_space*vm,Quoted 3 lines
drivers/gpu/drm/i915/i915_gem_gtt.c +1
-0list_add_tail (&vm->global_link, &dev_priv->vm_list); } +void gtt_write_workarounds (struct drm_device *dev) {Quoted 7 lines
Quoted 6 lines
static void
This can be squashed with 2/3.
-Mika
Do you mean all squashed together, into a single patch?
I would. They are all setting the same register to a nominal value, for the same purpose.
Quoted 6 lines
Quoted 2 lines
Don't we normally split WA into individual patches or is this only for this WA?
Is it not the same w/a applied to different generations? You either split it per device, so that a bisect + revert only affects one machine, or not all. Choose your poison.
yes but the value programmed is different for each device.
I think as Mika suggested, squashing 1, 2 which covers gen8 and another patch for gen9 is a good split.
regards
Arun
Quoted 2 lines
-Chris
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Re: [PATCH 1/3] drm/i915: add function for GT related workarounds
Quoted 70 lines
-----Original Message-----
From: Arun Siluvery [mailto:[email protected]]
Sent: Monday, January 25, 2016 6:04 PM
To: Chris Wilson; Gore, Tim; Mika Kuoppala; [email protected]
Subject: Re: [Intel-gfx] [PATCH 1/3] drm/i915: add function for GT related workaroundsQuoted 54 lines · Chris Wilson
Quoted 53 lines · Arun Siluvery
Quoted 51 lines · Chris Wilson
Quoted 40 lines · Tim
Tim Gore
Intel Corporation (UK) Ltd. - Co. Reg. #1134945 - Pipers Way, Swindon SN3 1RJQuoted 33 lines
-----Original Message-----
From: Mika Kuoppala [mailto:[email protected]]
Sent: Monday, January 25, 2016 2:39 PM
To: Gore, Tim; [email protected]
Cc: Gore, Tim; [email protected]
Subject: Re: [PATCH 1/3] drm/i915: add function for GT related workaroundsdrivers/gpu/drm/i915/i915_gem_gtt.c static void i915_address_space_init(struct
Quoted 18 lines · [email protected] writes:
From: Tim Gore <[email protected]>
Add a function that is a place for workarounds that are GT related but not required per ring. This function is called on driver load and also after a reset and on resume, so it is safe for workarounds that get clobbered in these situations.
Signed-off-by Tim Gore <[email protected]>--- drivers/gpu/drm/i915/i915_gem_gtt.c | 12 ++++++++++++ 1 file changed, 12 insertions(+)drivers/gpu/drm/i915/i915_gem_gtt.c +0
-0@@ -2132,6 +2132,16 @@ static void i915_address_space_init(struct
i915_address_space*vm,Quoted 3 lines
drivers/gpu/drm/i915/i915_gem_gtt.c +1
-0list_add_tail (&vm->global_link, &dev_priv->vm_list); } +void gtt_write_workarounds (struct drm_device *dev) {Quoted 7 lines
Quoted 6 lines
static void
This can be squashed with 2/3.
-Mika
Do you mean all squashed together, into a single patch?
I would. They are all setting the same register to a nominal value, for the same purpose.
Quoted 6 lines
Quoted 2 lines
Don't we normally split WA into individual patches or is this only for this WA?
Is it not the same w/a applied to different generations? You either split it per device, so that a bisect + revert only affects one machine, or not all. Choose your poison.
Quoted 8 lines
yes but the value programmed is different for each device.
I think as Mika suggested, squashing 1, 2 which covers gen8 and another patch for gen9 is a good split.
regards
Arun
I kept the introduction of the new w/a function as a separate patch so that the gen8 and gen9 patches are independent.
If you squash 1 and 2, then You can't revert just the gen8 changes because this would break the gen9 stuff.
Quoted 1 line
Tim Gore
Intel Corporation (UK) Ltd. - Co. Reg. #1134945 - Pipers Way, Swindon SN3 1RJ>
Quoted 3 lines
Quoted 3 lines
-Chris
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PATCH 2/3 drm/i915/gen8: add WaIncreaseDefaultTLBEntries
In reply to [email protected]From: Tim Gore <[email protected]>
Add WaIncreaseDefaultTLBEntries:chv,bdw.
This workaround provides significant perfromance boost for some OpenCL workloads by adjusting the L3_LRA_1_GPGPU register.
This is for bdw/chv. Further patches will provide the workaround for other sku's.
--- drivers/gpu/drm/i915/i915_gem_gtt.c | 5 +++++ drivers/gpu/drm/i915/i915_reg.h | 5 +++++ 2 files changed, 10 insertions(+)
drivers/gpu/drm/i915/i915_gem_gtt.c +5 -0
@@ -2140,6 +2140,11 @@ void gtt_write_workarounds(struct drm_device *dev)* called on driver load and after a GPU reset, so you can place * workarounds here even if they get overwritten by GPU reset. */ +/* WaIncreaseDefaultTLBEntries:chv,bdw */ +if (IS_BROADWELL (dev)) +I915_WRITE (GEN8_L3_LRA_1_GPGPU ,GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW ); +else if (IS_CHERRYVIEW (dev)) +I915_WRITE (GEN8_L3_LRA_1_GPGPU ,GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV ); }int i915_ppgtt_init (struct drm_device *dev,struct i915_hw_ppgtt *ppgtt)
drivers/gpu/drm/i915/i915_reg.h +5 -0
@@ -8159,4 +8159,9 @@ enum skl_disp_power_wells {#define GEN9_VEBOX_MOCS (i) _MMIO(0xcb00 + (i) * 4)/* Video MOCS registers */ #define GEN9_BLT_MOCS (i) _MMIO(0xcc00 + (i) * 4)/* Blitter MOCS registers */ +/* gamt regs */ +#define GEN8_L3_LRA_1_GPGPU _MMIO(0x4dd4) +#define GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW 0x67F1427F/* max/min for LRA1/2 */ +#define GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV 0x5FF101FF/* max/min for LRA1/2 */ +#endif /* _I915_REG_H_ */
Signature · 6 lines
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PATCH 3/3 drm/i915/gen9: add WaIncreaseDefaultTLBEntries
In reply to [email protected]From: Tim Gore <[email protected]>
Add WaIncreaseDefaultTLBEntries:skl,bxt.
This workaround provides significant perfromance boost for some OpenCL workloads by adjusting the L3_LRA_1_GPGPU register.
This is for skl/bxt. Further patches will provide the workaround for other sku's.
--- drivers/gpu/drm/i915/i915_gem_gtt.c | 4 ++++ drivers/gpu/drm/i915/i915_reg.h | 2 ++ 2 files changed, 6 insertions(+)
drivers/gpu/drm/i915/i915_gem_gtt.c +4 -0
@@ -2145,6 +2145,10 @@ void gtt_write_workarounds(struct drm_device *dev)I915_WRITE (GEN8_L3_LRA_1_GPGPU ,GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW ); else if (IS_CHERRYVIEW(dev)) I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV); + else if (IS_SKYLAKE(dev)) + I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL); + else if (IS_BROXTON(dev)) + I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT); }int i915_ppgtt_init (struct drm_device *dev,struct i915_hw_ppgtt *ppgtt)
drivers/gpu/drm/i915/i915_reg.h +2 -0
@@ -8163,5 +8163,7 @@ enum skl_disp_power_wells {#define GEN8_L3_LRA_1_GPGPU _MMIO(0x4dd4)#define GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW 0x67F1427F/* max/min for LRA1/2 */ #define GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV 0x5FF101FF/* max/min for LRA1/2 */ +#define GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL 0x67F1427F/* " " */ +#define GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT 0x5FF101FF/* " " */ #endif /* _I915_REG_H_ */
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Re: [PATCH 3/3] drm/i915/gen9: add WaIncreaseDefaultTLBEntries
Quoted 20 lines · [email protected] writes:
From: Tim Gore <[email protected]>
Add WaIncreaseDefaultTLBEntries:skl,bxt.
This workaround provides significant perfromance boost for some OpenCL workloads by adjusting theL3_LRA_1_GPGPUregister.
This is for skl/bxt. Further patches will provide the workaround for other sku's.Signed-off-by Tim Gore <[email protected]>--- drivers/gpu/drm/i915/i915_gem_gtt.c | 4 ++++ drivers/gpu/drm/i915/i915_reg.h | 2 ++ 2 files changed, 6 insertions(+)drivers/gpu/drm/i915/i915_gem_gtt.c +0
-0
drivers/gpu/drm/i915/i915_gem_gtt.c void gtt_write_workarounds(struct drm_device *dev) · line 2152
Quoted 8 lines
drivers/gpu/drm/i915/i915_gem_gtt.c +4
-0@@ -2145,6 +2145,10 @@ void gtt_write_workarounds(struct drm_device *dev)I915_WRITE (GEN8_L3_LRA_1_GPGPU ,GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW ); else if (IS_CHERRYVIEW(dev)) I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV); + else if (IS_SKYLAKE(dev)) + I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL); + else if (IS_BROXTON(dev)) + I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT); }
You forgot to add these to the Wa comment.
-Mika
Quoted 16 lines
drivers/gpu/drm/i915/i915_gem_gtt.c +0
-0int i915_ppgtt_init (struct drm_device *dev,struct i915_hw_ppgtt *ppgtt)drivers/gpu/drm/i915/i915_reg.h +2
-0@@ -8163,5 +8163,7 @@ enum skl_disp_power_wells {#define GEN8_L3_LRA_1_GPGPU _MMIO(0x4dd4)#define GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW 0x67F1427F/* max/min for LRA1/2 */ #define GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV 0x5FF101FF/* max/min for LRA1/2 */ +#define GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL 0x67F1427F/* " " */ +#define GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT 0x5FF101FF/* " " */ #endif /* _I915_REG_H_ */ Signature · 1 line
1.9.1
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Patchwork
CI✓ Fi.CI.BAT: success for drm/i915: add WaIncreaseDefaultTLBEntries
In reply to [email protected]== Summary ==
== Summary ==
Built on 5ae916607e3e12ba18c848dff42baaad5b118c4b drm-intel-nightly: 2016y-01m-27d-12h-48m-36s UTC integration manifest
bdw-nuci7 total:141 pass:132 dwarn:0 dfail:0 fail:0 skip:9 bdw-ultra total:144 pass:138 dwarn:0 dfail:0 fail:0 skip:6 bsw-nuc-2 total:144 pass:120 dwarn:0 dfail:0 fail:0 skip:24 hsw-brixbox total:144 pass:137 dwarn:0 dfail:0 fail:0 skip:7 hsw-gt2 total:144 pass:140 dwarn:0 dfail:0 fail:0 skip:4 ilk-hp8440p total:144 pass:105 dwarn:0 dfail:0 fail:1 skip:38 ivb-t430s total:144 pass:138 dwarn:0 dfail:0 fail:0 skip:6 skl-i5k-2 total:144 pass:135 dwarn:1 dfail:0 fail:0 skip:8 snb-dellxps total:144 pass:130 dwarn:0 dfail:0 fail:0 skip:14 snb-x220t total:144 pass:130 dwarn:0 dfail:0 fail:1 skip:13
Results at /archive/results/CI_IGT_test/Patchwork_1261/
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Patchwork
CI✓ Fi.CI.BAT: success for drm/i915: add WaIncreaseDefaultTLBEntries
In reply to [email protected]== Summary ==
== Summary ==
Series 2811v1 drm/i915: add WaIncreaseDefaultTLBEntries
Test kms_flip:
Subgroup basic-flip-vs-modeset:
pass -> DMESG-WARN (ilk-hp8440p) UNSTABLEbdw-nuci7 total:156 pass:147 dwarn:0 dfail:0 fail:0 skip:9 bdw-ultra total:159 pass:153 dwarn:0 dfail:0 fail:0 skip:6 bsw-nuc-2 total:159 pass:135 dwarn:0 dfail:0 fail:0 skip:24 byt-nuc total:159 pass:142 dwarn:0 dfail:0 fail:0 skip:17 hsw-brixbox total:159 pass:152 dwarn:0 dfail:0 fail:0 skip:7 hsw-gt2 total:159 pass:155 dwarn:0 dfail:0 fail:0 skip:4 ilk-hp8440p total:159 pass:113 dwarn:1 dfail:0 fail:1 skip:44 ivb-t430s total:159 pass:151 dwarn:0 dfail:0 fail:0 skip:8 skl-i5k-2 total:159 pass:150 dwarn:1 dfail:0 fail:0 skip:8 snb-dellxps total:159 pass:141 dwarn:0 dfail:0 fail:0 skip:18 snb-x220t total:159 pass:141 dwarn:0 dfail:0 fail:1 skip:17
Results at /archive/results/CI_IGT_test/Patchwork_1292/
HEAD is now at b3f8ad6 drm-intel-nightly: 2016y-01m-28d-10h-26m-23s UTC integration manifest
Applying: drm/i915: add function for GT related workarounds
Applying: drm/i915/gen8: add WaIncreaseDefaultTLBEntries
Applying: drm/i915/gen9: add WaIncreaseDefaultTLBEntries
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