perf/x86/msr: Add some new AMD performance event counters

PATCH In review Huang Rui 4 participants 8 messages Jan 29, 2016 – Mar 31, 2016

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x86 perf events

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Huang Rui

author

2016-01-29 08:30 UTC #0 lore raw

cover perf/x86/msr: Add some new AMD performance event counters

Hi all,

This serials of patches add two event counters that are PTSC (performance time-stamp counter) and IRperf (instructions retired count) for AMD new processors. They are incicated by CPUID.8000_0001H:ECX[27] and CPUID.8000_0008H:EBX[1] separately.

Thanks,
Rui

Huang Rui (2):
perf/x86/msr: Add AMD performance time-stamp counter support perf/x86/msr: Add AMD instructions retired performance counter

 arch/x86/include/asm/cpufeature.h    |  2 ++
 arch/x86/include/asm/msr-index.h     |  4 ++++
 arch/x86/kernel/cpu/perf_event_msr.c | 36 ++++++++++++++++++++++++++----------
 3 files changed, 32 insertions(+), 10 deletions(-)

Signature · 1 line

1.9.1

Huang Rui

author

2016-01-29 08:31 UTC #1 lore raw

PATCH 1/2 perf/x86/msr: Add AMD performance time-stamp counter support

AMD Carrizo (Family 15h, Model 60h) introduces a time-stamp counter which indicated by CPUID.8000_0001H:ECX[27]. It increments at a 100 MHz rate in all P-states, and C states, S0, or S1. The frequency is about 100MHz. This counter will be used for calculate processor power and other parts. So add an interface into MSR PMU to get the PTSC counter value.

Signed-off-by Huang Rui <[email protected]>

---
 arch/x86/include/asm/cpufeature.h    | 1 +
 arch/x86/include/asm/msr-index.h     | 1 +
 arch/x86/kernel/cpu/perf_event_msr.c | 8 ++++++++
 3 files changed, 10 insertions(+)

arch/x86/include/asm/cpufeature.h +1 -0

index f7ba9fb..1f9d682 100644
@@ -176,6 +176,7 @@
 #define X86_FEATURE_PERFCTR_CORE ( 6*32+23) /* core performance counter extensions */
 #define X86_FEATURE_PERFCTR_NB  ( 6*32+24) /* NB performance counter extensions */
 #define X86_FEATURE_BPEXT	(6*32+26) /* data breakpoint extension */
+#define X86_FEATURE_PTSC	( 6*32+27) /* performance time-stamp counter */
 #define X86_FEATURE_PERFCTR_L2	( 6*32+28) /* L2 performance counter extensions */
 #define X86_FEATURE_MWAITX	( 6*32+29) /* MWAIT extension (MONITORX/MWAITX) */

arch/x86/include/asm/msr-index.h +1 -0

index b05402e..0e873e3 100644
@@ -321,6 +321,7 @@
 #define MSR_F15H_PERF_CTR		0xc0010201
 #define MSR_F15H_NB_PERF_CTL		0xc0010240
 #define MSR_F15H_NB_PERF_CTR		0xc0010241
+#define MSR_F15H_PTSC			0xc0010280
 #define MSR_F15H_IC_CFG			0xc0011021
 
 /* Fam 10h MSRs */

arch/x86/kernel/cpu/perf_event_msr.c +8 -0

index ec863b9..6f6772f 100644
@@ -6,6 +6,7 @@ enum perf_msr_id {
 	PERF_MSR_MPERF			= 2,
 	PERF_MSR_PPERF			= 3,
 	PERF_MSR_SMI			= 4,
+	PERF_MSR_PTSC			= 5,
 
 	PERF_MSR_EVENT_MAX,
 };

@@ -15,6 +16,11 @@ static bool test_aperfmperf(int idx)
 	return boot_cpu_has(X86_FEATURE_APERFMPERF);
 }
 
+static bool test_ptsc(int idx)
+{
+	return boot_cpu_has(X86_FEATURE_PTSC);
+}
+
 static bool test_intel(int idx)
 {
 	if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL ||

@@ -74,6 +80,7 @@ PMU_EVENT_ATTR_STRING(aperf, evattr_aperf, "event=0x01");
 PMU_EVENT_ATTR_STRING(mperf, evattr_mperf, "event=0x02");
 PMU_EVENT_ATTR_STRING(pperf, evattr_pperf, "event=0x03");
 PMU_EVENT_ATTR_STRING(smi,   evattr_smi,   "event=0x04");
+PMU_EVENT_ATTR_STRING(ptsc,  evattr_ptsc,  "event=0x05");
 
 static struct perf_msr msr[] = {
 	[PERF_MSR_TSC]   = { 0,			&evattr_tsc,	NULL,		 },

@@ -81,6 +88,7 @@ static struct perf_msr msr[] = {
 	[PERF_MSR_MPERF] = { MSR_IA32_MPERF,	&evattr_mperf,	test_aperfmperf, },
 	[PERF_MSR_PPERF] = { MSR_PPERF,		&evattr_pperf,	test_intel,	 },
 	[PERF_MSR_SMI]   = { MSR_SMI_COUNT,	&evattr_smi,	test_intel,	 },
+	[PERF_MSR_PTSC]   = { MSR_F15H_PTSC,	&evattr_ptsc,	test_ptsc,	 },
 };
 
 static struct attribute *events_attrs[PERF_MSR_EVENT_MAX + 1] = {

Signature · 1 line

1.9.1

tip-bot for Huang Rui

merge bot

2016-03-31 09:23 UTC #2 lore raw

[tip:perf/core] perf/x86/msr: Add AMD PTSC (Performance Time-Stamp Counter) support

perf/x86/msr: Add AMD PTSC (Performance Time-Stamp Counter) support

Commit-ID:  8a22426184774d7ced9c1d3aa4d95d34101fb3be
Gitweb:     http://git.kernel.org/tip/8a22426184774d7ced9c1d3aa4d95d34101fb3be
Author:     Huang Rui <[email protected]>
AuthorDate: Fri, 29 Jan 2016 16:29:56 +0800
Committer:  Ingo Molnar <[email protected]>
CommitDate: Thu, 31 Mar 2016 10:30:39 +0200

perf/x86/msr: Add AMD PTSC (Performance Time-Stamp Counter) support

AMD Carrizo (Family 15h, Model 60h) introduces a time-stamp counter which is indicated by CPUID.8000_0001H:ECX[27]. It increments at a 100 MHz rate in all P-states, and C states, S0, or S1. The frequency is about 100MHz. This counter will be used to calculate processor power and other parts. So add an interface into the MSR PMU to get the PTSC counter value.

Signed-off-by Huang Rui <[email protected]>

Signed-off-by Peter Zijlstra (Intel) <[email protected]>

Cc Alexander Shishkin <[email protected]>

Cc Andy Lutomirski <[email protected]>

Cc Aravind Gopalakrishnan <[email protected]>

Cc Arnaldo Carvalho de Melo <[email protected]>

Cc Borislav Petkov <[email protected]>

Cc Fengguang Wu <[email protected]>

Cc Jacob Shin <[email protected]>

Cc Jiri Olsa <[email protected]>

Cc Kan Liang <[email protected]>

Cc Linus Torvalds <[email protected]>

Cc Peter Zijlstra <[email protected]>

Cc Robert Richter <[email protected]>

Cc Stephane Eranian <[email protected]>

Cc Suravee Suthikulpanit <[email protected]>

Cc Thomas Gleixner <[email protected]>

Cc Vince Weaver <[email protected]>

Link http://lkml.kernel.org/r/[email protected] open here

Signed-off-by Ingo Molnar <[email protected]>

---
 arch/x86/events/msr.c              | 8 ++++++++
 arch/x86/include/asm/cpufeatures.h | 1 +
 arch/x86/include/asm/msr-index.h   | 1 +
 3 files changed, 10 insertions(+)

arch/x86/events/msr.c +8 -0

index ec863b9..6f6772f 100644
@@ -6,6 +6,7 @@ enum perf_msr_id {
 	PERF_MSR_MPERF			= 2,
 	PERF_MSR_PPERF			= 3,
 	PERF_MSR_SMI			= 4,
+	PERF_MSR_PTSC			= 5,
 
 	PERF_MSR_EVENT_MAX,
 };

@@ -15,6 +16,11 @@ static bool test_aperfmperf(int idx)
 	return boot_cpu_has(X86_FEATURE_APERFMPERF);
 }
 
+static bool test_ptsc(int idx)
+{
+	return boot_cpu_has(X86_FEATURE_PTSC);
+}
+
 static bool test_intel(int idx)
 {
 	if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL ||

@@ -74,6 +80,7 @@ PMU_EVENT_ATTR_STRING(aperf, evattr_aperf, "event=0x01");
 PMU_EVENT_ATTR_STRING(mperf, evattr_mperf, "event=0x02");
 PMU_EVENT_ATTR_STRING(pperf, evattr_pperf, "event=0x03");
 PMU_EVENT_ATTR_STRING(smi,   evattr_smi,   "event=0x04");
+PMU_EVENT_ATTR_STRING(ptsc,  evattr_ptsc,  "event=0x05");
 
 static struct perf_msr msr[] = {
 	[PERF_MSR_TSC]   = { 0,			&evattr_tsc,	NULL,		 },

@@ -81,6 +88,7 @@ static struct perf_msr msr[] = {
 	[PERF_MSR_MPERF] = { MSR_IA32_MPERF,	&evattr_mperf,	test_aperfmperf, },
 	[PERF_MSR_PPERF] = { MSR_PPERF,		&evattr_pperf,	test_intel,	 },
 	[PERF_MSR_SMI]   = { MSR_SMI_COUNT,	&evattr_smi,	test_intel,	 },
+	[PERF_MSR_PTSC]   = { MSR_F15H_PTSC,	&evattr_ptsc,	test_ptsc,	 },
 };
 
 static struct attribute *events_attrs[PERF_MSR_EVENT_MAX + 1] = {

arch/x86/include/asm/cpufeatures.h +1 -0

index 44ebd04..bdf9042 100644
@@ -177,6 +177,7 @@
 #define X86_FEATURE_PERFCTR_CORE ( 6*32+23) /* core performance counter extensions */
 #define X86_FEATURE_PERFCTR_NB  ( 6*32+24) /* NB performance counter extensions */
 #define X86_FEATURE_BPEXT	(6*32+26) /* data breakpoint extension */
+#define X86_FEATURE_PTSC	( 6*32+27) /* performance time-stamp counter */
 #define X86_FEATURE_PERFCTR_L2	( 6*32+28) /* L2 performance counter extensions */
 #define X86_FEATURE_MWAITX	( 6*32+29) /* MWAIT extension (MONITORX/MWAITX) */

arch/x86/include/asm/msr-index.h +1 -0

index 984ab75..6e6a5cc 100644
@@ -326,6 +326,7 @@
 #define MSR_F15H_PERF_CTR		0xc0010201
 #define MSR_F15H_NB_PERF_CTL		0xc0010240
 #define MSR_F15H_NB_PERF_CTR		0xc0010241
+#define MSR_F15H_PTSC			0xc0010280
 #define MSR_F15H_IC_CFG			0xc0011021
 
 /* Fam 10h MSRs */

Huang Rui

author

2016-01-29 08:31 UTC #3 lore raw

PATCH 2/2 perf/x86/msr: Add AMD instructions retired performance counter

In reply to Huang Rui

AMD Zeppelin (Family 17h, Model 00h) introduces an instructions retired performance counter which indicated by CPUID.8000_0008H:EBX[1]. And dedicated Instructions Retired register (MSR 0xC000_000E9) increments on once for every instruction retired.

Signed-off-by Huang Rui <[email protected]>

---
 arch/x86/include/asm/cpufeature.h    |  1 +
 arch/x86/include/asm/msr-index.h     |  3 +++
 arch/x86/kernel/cpu/perf_event_msr.c | 30 +++++++++++++++++++-----------
 3 files changed, 23 insertions(+), 11 deletions(-)

arch/x86/include/asm/cpufeature.h +1 -0

index 1f9d682..a0ec7cc 100644
@@ -259,6 +259,7 @@
 
 /* AMD-defined CPU features, CPUID level 0x80000008 (ebx), word 13 */
 #define X86_FEATURE_CLZERO	(13*32+0) /* CLZERO instruction */
+#define X86_FEATURE_IRPERF	(13*32+1) /* Instructions Retired Count */
 
 /*
  * BUG word(s)

arch/x86/include/asm/msr-index.h +3 -0

index 0e873e3..982dcda 100644
@@ -308,6 +308,9 @@
 #define MSR_AMD64_IBSOPDATA4		0xc001103d
 #define MSR_AMD64_IBS_REG_COUNT_MAX	8 /* includes MSR_AMD64_IBSBRTARGET */
 
+/* Fam 17h MSRs */
+#define MSR_F17H_IRPERF			0xc00000e9
+
 /* Fam 16h MSRs */
 #define MSR_F16H_L2I_PERF_CTL		0xc0010230
 #define MSR_F16H_L2I_PERF_CTR		0xc0010231

arch/x86/kernel/cpu/perf_event_msr.c +19 ~~-11~~

index 6f6772f..7111400 100644
@@ -7,6 +7,7 @@ enum perf_msr_id {
 	PERF_MSR_PPERF			= 3,
 	PERF_MSR_SMI			= 4,
 	PERF_MSR_PTSC			= 5,
+	PERF_MSR_IRPERF			= 6,
 
 	PERF_MSR_EVENT_MAX,
 };

@@ -21,6 +22,11 @@ static bool test_ptsc(int idx)
 	return boot_cpu_has(X86_FEATURE_PTSC);
 }
 
+static bool test_irperf(int idx)
+{
+	return boot_cpu_has(X86_FEATURE_IRPERF);
+}
+
 static bool test_intel(int idx)
 {
 	if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL ||

@@ -75,20 +81,22 @@ struct perf_msr {
 	bool	(*test)(int idx);
 };
 
-PMU_EVENT_ATTR_STRING(tsc,   evattr_tsc,   "event=0x00");
-PMU_EVENT_ATTR_STRING(aperf, evattr_aperf, "event=0x01");
-PMU_EVENT_ATTR_STRING(mperf, evattr_mperf, "event=0x02");
-PMU_EVENT_ATTR_STRING(pperf, evattr_pperf, "event=0x03");
-PMU_EVENT_ATTR_STRING(smi,   evattr_smi,   "event=0x04");
-PMU_EVENT_ATTR_STRING(ptsc,  evattr_ptsc,  "event=0x05");
+PMU_EVENT_ATTR_STRING(tsc,    evattr_tsc,    "event=0x00");
+PMU_EVENT_ATTR_STRING(aperf,  evattr_aperf,  "event=0x01");
+PMU_EVENT_ATTR_STRING(mperf,  evattr_mperf,  "event=0x02");
+PMU_EVENT_ATTR_STRING(pperf,  evattr_pperf,  "event=0x03");
+PMU_EVENT_ATTR_STRING(smi,    evattr_smi,    "event=0x04");
+PMU_EVENT_ATTR_STRING(ptsc,   evattr_ptsc,   "event=0x05");
+PMU_EVENT_ATTR_STRING(irperf, evattr_irperf, "event=0x06");
 
 static struct perf_msr msr[] = {
-	[PERF_MSR_TSC]   = { 0,			&evattr_tsc,	NULL,		 },
-	[PERF_MSR_APERF] = { MSR_IA32_APERF,	&evattr_aperf,	test_aperfmperf, },
-	[PERF_MSR_MPERF] = { MSR_IA32_MPERF,	&evattr_mperf,	test_aperfmperf, },
-	[PERF_MSR_PPERF] = { MSR_PPERF,		&evattr_pperf,	test_intel,	 },
-	[PERF_MSR_SMI]   = { MSR_SMI_COUNT,	&evattr_smi,	test_intel,	 },
+	[PERF_MSR_TSC]    = { 0,		&evattr_tsc,	NULL,		 },
+	[PERF_MSR_APERF]  = { MSR_IA32_APERF,	&evattr_aperf,	test_aperfmperf, },
+	[PERF_MSR_MPERF]  = { MSR_IA32_MPERF,	&evattr_mperf,	test_aperfmperf, },
+	[PERF_MSR_PPERF]  = { MSR_PPERF,	&evattr_pperf,	test_intel,	 },
+	[PERF_MSR_SMI]    = { MSR_SMI_COUNT,	&evattr_smi,	test_intel,	 },
 	[PERF_MSR_PTSC]   = { MSR_F15H_PTSC,	&evattr_ptsc,	test_ptsc,	 },
+	[PERF_MSR_IRPERF] = { MSR_F17H_IRPERF,	&evattr_irperf,	test_irperf,	 },
 };
 
 static struct attribute *events_attrs[PERF_MSR_EVENT_MAX + 1] = {

Signature · 1 line

1.9.1

tip-bot for Huang Rui

merge bot

2016-03-31 09:23 UTC #4 lore raw

[tip:perf/core] perf/x86/msr: Add AMD IRPERF (Instructions Retired) performance counter

perf/x86/msr: Add AMD IRPERF (Instructions Retired) performance counter

Commit-ID:  aaf248848db503927644d28e239bc399ed45959f
Gitweb:     http://git.kernel.org/tip/aaf248848db503927644d28e239bc399ed45959f
Author:     Huang Rui <[email protected]>
AuthorDate: Fri, 29 Jan 2016 16:29:57 +0800
Committer:  Ingo Molnar <[email protected]>
CommitDate: Thu, 31 Mar 2016 10:30:39 +0200

perf/x86/msr: Add AMD IRPERF (Instructions Retired) performance counter

AMD Zeppelin (Family 17h, Model 00h) introduces an instructions retired performance counter which is indicated by CPUID.8000_0008H:EBX[1]. A dedicated Instructions Retired MSR register (MSR 0xC000_000E9) increments once for every instruction retired.

Signed-off-by Huang Rui <[email protected]>

Signed-off-by Peter Zijlstra (Intel) <[email protected]>

Cc Alexander Shishkin <[email protected]>

Cc Andy Lutomirski <[email protected]>

Cc Aravind Gopalakrishnan <[email protected]>

Cc Arnaldo Carvalho de Melo <[email protected]>

Cc Borislav Petkov <[email protected]>

Cc Fengguang Wu <[email protected]>

Cc Jacob Shin <[email protected]>

Cc Jiri Olsa <[email protected]>

Cc Kan Liang <[email protected]>

Cc Linus Torvalds <[email protected]>

Cc Peter Zijlstra <[email protected]>

Cc Robert Richter <[email protected]>

Cc Stephane Eranian <[email protected]>

Cc Suravee Suthikulpanit <[email protected]>

Cc Thomas Gleixner <[email protected]>

Cc Vince Weaver <[email protected]>

Link http://lkml.kernel.org/r/[email protected] open here

Signed-off-by Ingo Molnar <[email protected]>

---
 arch/x86/events/msr.c              | 30 +++++++++++++++++++-----------
 arch/x86/include/asm/cpufeatures.h |  1 +
 arch/x86/include/asm/msr-index.h   |  3 +++
 3 files changed, 23 insertions(+), 11 deletions(-)

arch/x86/events/msr.c +19 ~~-11~~

index 6f6772f..7111400 100644
@@ -7,6 +7,7 @@ enum perf_msr_id {
 	PERF_MSR_PPERF			= 3,
 	PERF_MSR_SMI			= 4,
 	PERF_MSR_PTSC			= 5,
+	PERF_MSR_IRPERF			= 6,
 
 	PERF_MSR_EVENT_MAX,
 };

@@ -21,6 +22,11 @@ static bool test_ptsc(int idx)
 	return boot_cpu_has(X86_FEATURE_PTSC);
 }
 
+static bool test_irperf(int idx)
+{
+	return boot_cpu_has(X86_FEATURE_IRPERF);
+}
+
 static bool test_intel(int idx)
 {
 	if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL ||

@@ -75,20 +81,22 @@ struct perf_msr {
 	bool	(*test)(int idx);
 };
 
-PMU_EVENT_ATTR_STRING(tsc,   evattr_tsc,   "event=0x00");
-PMU_EVENT_ATTR_STRING(aperf, evattr_aperf, "event=0x01");
-PMU_EVENT_ATTR_STRING(mperf, evattr_mperf, "event=0x02");
-PMU_EVENT_ATTR_STRING(pperf, evattr_pperf, "event=0x03");
-PMU_EVENT_ATTR_STRING(smi,   evattr_smi,   "event=0x04");
-PMU_EVENT_ATTR_STRING(ptsc,  evattr_ptsc,  "event=0x05");
+PMU_EVENT_ATTR_STRING(tsc,    evattr_tsc,    "event=0x00");
+PMU_EVENT_ATTR_STRING(aperf,  evattr_aperf,  "event=0x01");
+PMU_EVENT_ATTR_STRING(mperf,  evattr_mperf,  "event=0x02");
+PMU_EVENT_ATTR_STRING(pperf,  evattr_pperf,  "event=0x03");
+PMU_EVENT_ATTR_STRING(smi,    evattr_smi,    "event=0x04");
+PMU_EVENT_ATTR_STRING(ptsc,   evattr_ptsc,   "event=0x05");
+PMU_EVENT_ATTR_STRING(irperf, evattr_irperf, "event=0x06");
 
 static struct perf_msr msr[] = {
-	[PERF_MSR_TSC]   = { 0,			&evattr_tsc,	NULL,		 },
-	[PERF_MSR_APERF] = { MSR_IA32_APERF,	&evattr_aperf,	test_aperfmperf, },
-	[PERF_MSR_MPERF] = { MSR_IA32_MPERF,	&evattr_mperf,	test_aperfmperf, },
-	[PERF_MSR_PPERF] = { MSR_PPERF,		&evattr_pperf,	test_intel,	 },
-	[PERF_MSR_SMI]   = { MSR_SMI_COUNT,	&evattr_smi,	test_intel,	 },
+	[PERF_MSR_TSC]    = { 0,		&evattr_tsc,	NULL,		 },
+	[PERF_MSR_APERF]  = { MSR_IA32_APERF,	&evattr_aperf,	test_aperfmperf, },
+	[PERF_MSR_MPERF]  = { MSR_IA32_MPERF,	&evattr_mperf,	test_aperfmperf, },
+	[PERF_MSR_PPERF]  = { MSR_PPERF,	&evattr_pperf,	test_intel,	 },
+	[PERF_MSR_SMI]    = { MSR_SMI_COUNT,	&evattr_smi,	test_intel,	 },
 	[PERF_MSR_PTSC]   = { MSR_F15H_PTSC,	&evattr_ptsc,	test_ptsc,	 },
+	[PERF_MSR_IRPERF] = { MSR_F17H_IRPERF,	&evattr_irperf,	test_irperf,	 },
 };
 
 static struct attribute *events_attrs[PERF_MSR_EVENT_MAX + 1] = {

arch/x86/include/asm/cpufeatures.h +1 -0

index bdf9042..dd448a9 100644
@@ -251,6 +251,7 @@
 
 /* AMD-defined CPU features, CPUID level 0x80000008 (ebx), word 13 */
 #define X86_FEATURE_CLZERO	(13*32+0) /* CLZERO instruction */
+#define X86_FEATURE_IRPERF	(13*32+1) /* Instructions Retired Count */
 
 /* Thermal and Power Management Leaf, CPUID level 0x00000006 (eax), word 14 */
 #define X86_FEATURE_DTHERM	(14*32+ 0) /* Digital Thermal Sensor */

arch/x86/include/asm/msr-index.h +3 -0

index 6e6a5cc..e0e2f7d 100644
@@ -313,6 +313,9 @@
 #define MSR_AMD64_IBSOPDATA4		0xc001103d
 #define MSR_AMD64_IBS_REG_COUNT_MAX	8 /* includes MSR_AMD64_IBSBRTARGET */
 
+/* Fam 17h MSRs */
+#define MSR_F17H_IRPERF			0xc00000e9
+
 /* Fam 16h MSRs */
 #define MSR_F16H_L2I_PERF_CTL		0xc0010230
 #define MSR_F16H_L2I_PERF_CTR		0xc0010231

Huang Rui

author

2016-03-21 10:09 UTC #5 lore raw

In reply to Huang Rui

Quoted 10 lines · Huang Rui

Hi all,
This serials of patches add two event counters that are PTSC (performance time-stamp counter) and IRperf (instructions retired count) for AMD new processors. They are incicated by CPUID.8000_0001H:ECX[27] and CPUID.8000_0008H:EBX[1] separately.
Thanks,
Rui

Quoted 9 lines

Huang Rui (2):
perf/x86/msr: Add AMD performance time-stamp counter support perf/x86/msr: Add AMD instructions retired performance counter
 arch/x86/include/asm/cpufeature.h    |  2 ++
 arch/x86/include/asm/msr-index.h     |  4 ++++
 arch/x86/kernel/cpu/perf_event_msr.c | 36 ++++++++++++++++++++++++++----------
 3 files changed, 32 insertions(+), 10 deletions(-)

Hi Ingo, Peter, Boris,

Can you apply these two patches since I sent two months before. Need I rebase them?

Thanks,
Rui

Borislav Petkov

maintainer

2016-03-21 10:31 UTC #6 lore raw

Quoted 2 lines · Huang Rui

Can you apply these two patches since I sent two months before. Need I rebase them?

Yes, please rebase and test them ontop of 4.6-rc1 once Linus releases it at the end of this/beginning of next week.

Thanks.

Signature · 4 lines

Regards/Gruss,
    Boris.

ECO tip #101: Trim your mails when you reply.

Peter Zijlstra

maintainer

2016-03-21 12:40 UTC #7 lore raw

Quoted 6 lines · Borislav Petkov

Quoted 2 lines · Huang Rui
Can you apply these two patches since I sent two months before. Need I rebase them?
Yes, please rebase and test them ontop of 4.6-rc1 once Linus releases it at the end of this/beginning of next week.

No need, I stomped on them and now they fit again.