ARM: keystone2: Miscellaneous fixes

index edebcd7bc587..8ca19bbcdbe9 100644
@@ -160,6 +160,7 @@ typedef volatile unsigned int   *dv_reg_p;
 #define KS2_LPSC_GEM_0			15
 #define KS2_LPSC_TETRIS			52
 #define KS2_TETRIS_PWR_DOMAIN		31
+#define KS2_GEM_0_PWR_DOMAIN		8
 
 /* Chip configuration unlock codes and registers */
 #define KS2_KICK0			(KS2_DEVICE_STATE_CTRL_BASE + 0x38)

index 11a9357db414..a8071270e9bf 100644
@@ -54,7 +54,7 @@ static void turn_off_all_dsps(int num_dsps)
 		if (psc_disable_module(i + KS2_LPSC_GEM_0))
 			printf("Cannot disable module for #%d DSP", i);
 
-		if (psc_disable_domain(i + 8))
+		if (psc_disable_domain(i + KS2_GEM_0_PWR_DOMAIN))
 			printf("Cannot disable domain for #%d DSP", i);
 	}
 }

index fa4162fe9964..ca2a119d3901 100644
@@ -10,7 +10,7 @@
 #ifndef __ASM_ARCH_HARDWARE_K2G_H
 #define __ASM_ARCH_HARDWARE_K2G_H
 
-#define KS2_NUM_DSPS	0
+#define KS2_NUM_DSPS			1
 
 /* Power and Sleep Controller (PSC) Domains */
 #define KS2_LPSC_ALWAYSON		0

@@ -30,7 +30,10 @@
 #define KS2_LPSC_MCASP			15
 #define KS2_LPSC_SR			16
 #define KS2_LPSC_MSMC			17
-#define KS2_LPSC_GEM			18
+#ifdef KS2_LPSC_GEM_0
+#undef KS2_LPSC_GEM_0
+#endif
+#define KS2_LPSC_GEM_0			18
 #define KS2_LPSC_ARM			19
 #define KS2_LPSC_ASRC			20
 #define KS2_LPSC_ICSS			21

index 5c6051e76db8..1ae3baf982a1 100644
@@ -228,14 +228,14 @@ void init_plls(void)
 	}
 }
 
-static int get_max_speed(u32 val, u32 speed_supported)
+static int get_max_speed(u32 val, u32 speed_supported, int *spds)
 {
 	int speed;
 
 	/* Left most setbit gives the speed */
 	for (speed = DEVSPEED_NUMSPDS; speed >= 0; speed--) {
 		if ((val & BIT(speed)) & speed_supported)
-			return speeds[speed];
+			return spds[speed];
 	}
 
 	/* If no bit is set, use SPD800 */

@@ -250,24 +250,24 @@ static inline u32 read_efuse_bootrom(void)
 		return __raw_readl(KS2_EFUSE_BOOTROM);
 }
 
-int get_max_arm_speed(void)
+int get_max_arm_speed(int *spds)
 {
 	u32 armspeed = read_efuse_bootrom();
 
 	armspeed = (armspeed & DEVSPEED_ARMSPEED_MASK) >>
 		    DEVSPEED_ARMSPEED_SHIFT;
 
-	return get_max_speed(armspeed, ARM_SUPPORTED_SPEEDS);
+	return get_max_speed(armspeed, ARM_SUPPORTED_SPEEDS, spds);
 }
 
-int get_max_dev_speed(void)
+int get_max_dev_speed(int *spds)
 {
 	u32 devspeed = read_efuse_bootrom();
 
 	devspeed = (devspeed & DEVSPEED_DEVSPEED_MASK) >>
 		    DEVSPEED_DEVSPEED_SHIFT;
 
-	return get_max_speed(devspeed, DEV_SUPPORTED_SPEEDS);
+	return get_max_speed(devspeed, DEV_SUPPORTED_SPEEDS, spds);
 }
 
 /**

index cdcff3baee36..dfebcb03ea57 100644
@@ -124,8 +124,8 @@ struct pll_init_data *get_pll_init_data(int pll);
 unsigned long clk_get_rate(unsigned int clk);
 unsigned long clk_round_rate(unsigned int clk, unsigned long hz);
 int clk_set_rate(unsigned int clk, unsigned long hz);
-int get_max_dev_speed(void);
-int get_max_arm_speed(void);
+int get_max_dev_speed(int *spds);
+int get_max_arm_speed(int *spds);
 void pll_pa_clk_sel(void);
 
 #endif

index f58f62358d3e..cbb3077bc36c 100644
@@ -61,7 +61,7 @@ struct pll_init_data *get_pll_init_data(int pll)
 
 	switch (pll) {
 	case MAIN_PLL:
-		speed = get_max_dev_speed();
+		speed = get_max_dev_speed(speeds);
 		data = &core_pll_config[speed];
 		break;
 	case PASS_PLL:

index 0bd6b86e2573..e217beaed5e4 100644
@@ -51,11 +51,11 @@ struct pll_init_data *get_pll_init_data(int pll)
 
 	switch (pll) {
 	case MAIN_PLL:
-		speed = get_max_dev_speed();
+		speed = get_max_dev_speed(speeds);
 		data = &core_pll_config[speed];
 		break;
 	case TETRIS_PLL:
-		speed = get_max_arm_speed();
+		speed = get_max_arm_speed(speeds);
 		data = &tetris_pll_config[speed];
 		break;
 	case PASS_PLL:

index d750ad3c0b05..2a2e0057e24e 100644
@@ -50,11 +50,11 @@ struct pll_init_data *get_pll_init_data(int pll)
 
 	switch (pll) {
 	case MAIN_PLL:
-		speed = get_max_dev_speed();
+		speed = get_max_dev_speed(speeds);
 		data = &core_pll_config[speed];
 		break;
 	case TETRIS_PLL:
-		speed = get_max_arm_speed();
+		speed = get_max_arm_speed(speeds);
 		data = &tetris_pll_config[speed];
 		break;
 	case PASS_PLL:

index 1ae3baf982a1..b25db1e3fede 100644
@@ -238,8 +238,11 @@ static int get_max_speed(u32 val, u32 speed_supported, int *spds)
 			return spds[speed];
 	}
 
-	/* If no bit is set, use SPD800 */
-	return SPD800;
+	/* If no bit is set, return minimum speed */
+	if (cpu_is_k2g())
+		return SPD200;
+	else
+		return SPD800;
 }
 
 static inline u32 read_efuse_bootrom(void)

index 214c1d3a8360..74de6202fe50 100644
@@ -12,8 +12,8 @@
 
 #define PLLSET_CMD_LIST		"<pa|arm|ddr3>"
 
-#define DEV_SUPPORTED_SPEEDS	0xfff
-#define ARM_SUPPORTED_SPEEDS	0xfff
+#define DEV_SUPPORTED_SPEEDS	0x1ff
+#define ARM_SUPPORTED_SPEEDS	0xff
 
 #define KS2_CLK1_6 sys_clk0_6_clk
 

index dfebcb03ea57..72724aa4a912 100644
@@ -63,8 +63,12 @@
 #define CLOCK_INDEXES_LIST	CLK_LIST(GENERATE_INDX_STR)
 
 enum {
+	SPD200,
+	SPD400,
+	SPD600,
 	SPD800,
 	SPD850,
+	SPD900,
 	SPD1000,
 	SPD1200,
 	SPD1250,

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index a22c237c8026..68d3cb4245e9 100644
@@ -48,6 +48,14 @@ struct ddr3_emif_config {
 	unsigned int sdrfc;
 };
 
+struct ddr3_spd_cb {
+	char   dimm_name[32];
+	struct ddr3_phy_config phy_cfg;
+	struct ddr3_emif_config emif_cfg;
+	unsigned int ddrspdclock;
+	int    ddr_size_gbyte;
+};
+
 u32 ddr3_init(void);
 void ddr3_reset_ddrphy(void);
 void ddr3_init_ecc(u32 base, u32 ddr3_size);

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index 5bd786cff8e9..f95eddec3308 100644
@@ -10,18 +10,11 @@
 #ifndef __DDR3_CFG_H
 #define __DDR3_CFG_H
 
-extern struct ddr3_phy_config ddr3phy_1600_8g;
-extern struct ddr3_emif_config ddr3_1600_8g;
-
-extern struct ddr3_phy_config ddr3phy_1333_2g;
-extern struct ddr3_emif_config ddr3_1333_2g;
-
-extern struct ddr3_phy_config ddr3phy_1600_4g;
-extern struct ddr3_emif_config ddr3_1600_4g;
+#include <asm/arch/ddr3.h>
 
 extern struct ddr3_phy_config ddr3phy_1600_2g;
 extern struct ddr3_emif_config ddr3_1600_2g;
 
-int ddr3_get_dimm_params(char *dimm_name);
+int ddr3_get_dimm_params_from_spd(struct ddr3_spd_cb *spd_cb);
 
 #endif /* __DDR3_CFG_H */

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index 4f4ebf53ec59..e053a54d4169 100644
@@ -38,4 +38,6 @@
 #define CONFIG_KSNET_CPSW_NUM_PORTS	9
 #define CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE
 
+#define CONFIG_DDR_SPD
+
 #endif /* __CONFIG_K2E_EVM_H */

index 6c6dcb1e5ed3..3cd2a85a2d11 100644
@@ -37,4 +37,6 @@
 #define CONFIG_KSNET_NETCP_V1_0
 #define CONFIG_KSNET_CPSW_NUM_PORTS	5
 
+#define CONFIG_DDR_SPD
+
 #endif /* __CONFIG_K2HK_EVM_H */

index b0768823f2eb..a99b7728cefb 100644
@@ -427,6 +427,16 @@ static int ddr3_read_spd(ddr3_spd_eeprom_t *spd_params)
 	return 0;
 }
 
+int ddr3_get_size(void)
+{
+	ddr3_spd_eeprom_t spd_params;
+
+	if (ddr3_read_spd(&spd_params))
+		return 0;
+
+	return ddr3_get_size_in_mb(&spd_params) / 1024;
+}
+
 int ddr3_get_dimm_params_from_spd(struct ddr3_spd_cb *spd_cb)
 {
 	struct ddr3_sodimm spd;

index 68d3cb4245e9..5feffe825b97 100644
@@ -66,5 +66,6 @@ void ddr3_err_reset_workaround(void);
 void ddr3_enable_ecc(u32 base, int test);
 void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg);
 void ddr3_init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg);
+int ddr3_get_size(void);
 
 #endif

index 4f1197ea923d..a59e0713593f 100644
@@ -105,4 +105,11 @@
 /* NETCP */
 #define KS2_NETCP_BASE			0x26000000
 
+#ifndef __ASSEMBLY__
+static inline int ddr3_get_size(void)
+{
+	return 2;
+}
+#endif
+
 #endif /* __ASM_ARCH_HARDWARE_K2L_H */

index 7d1709c880af..ca668a7c6902 100644
@@ -146,9 +146,7 @@ int ft_board_setup(void *blob, bd_t *bd)
 
 	ddr3a_size = 0;
 	if (lpae) {
-		env = getenv("ddr3a_size");
-		if (env)
-			ddr3a_size = simple_strtol(env, NULL, 10);
+		ddr3a_size = ddr3_get_size();
 		if ((ddr3a_size != 8) && (ddr3a_size != 4))
 			ddr3a_size = 0;
 	}