x86/cpufeatures.h: Enumerate A Few New AVX-512 Features
PATCH 1/1 x86/cpufeatures.h: Enumerate A Few New AVX-512 Features
From: Fenghua Yu <[email protected]>
A few new AVX-512 instruction groups/features are added in cpufeatures.h for enuermation: AVX512DQ, AVX512BW, and AVX512VL.
The specification for latest AVX-512 including the features can be found at
https://software.intel.com/sites/default/files/managed/07/b7/319433-023.pdf
--- arch/x86/include/asm/cpufeature.h | 3 +++ 1 file changed, 3 insertions(+)
arch/x86/include/asm/cpufeature.h +3 -0
@@ -219,6 +219,7 @@#define X86_FEATURE_CQM ( 9*32+12)/* Cache QoS Monitoring */ #define X86_FEATURE_MPX ( 9*32+14)/* Memory Protection Extension */ #define X86_FEATURE_AVX512F ( 9*32+16)/* AVX-512 Foundation */ +#define X86_FEATURE_AVX512DQ ( 9*32+17)/* AVX-512 DQ Instructions */ #define X86_FEATURE_RDSEED ( 9*32+18)/* The RDSEED instruction */ #define X86_FEATURE_ADX ( 9*32+19)/* The ADCX and ADOX instructions */ #define X86_FEATURE_SMAP ( 9*32+20)/* Supervisor Mode Access Prevention */
@@ -229,6 +230,8 @@#define X86_FEATURE_AVX512ER ( 9*32+27)/* AVX-512 Exponential and Reciprocal */ #define X86_FEATURE_AVX512CD ( 9*32+28)/* AVX-512 Conflict Detection */ #define X86_FEATURE_SHA_NI ( 9*32+29)/* SHA1/SHA256 Instruction Extensions */ +#define X86_FEATURE_AVX512BW ( 9*32+30)/* AVX-512 BW Instructions */ +#define X86_FEATURE_AVX512VL ( 9*32+31)/* AVX-512 Vector Lengths */ /* Extended state features, CPUID level 0x0000000d:1 (eax), word 10 */ #define X86_FEATURE_XSAVEOPT (10*32+ 0)/* XSAVEOPT */
Signature · 1 line
2.5.0
Quoted 26 lines · Fenghua Yu
From: Fenghua Yu <[email protected]>
A few new AVX-512 instruction groups/features are added in
cpufeatures.hfor enuermation: AVX512DQ, AVX512BW, and AVX512VL.The specification for latest AVX-512 including the features can be found at
https://software.intel.com/sites/default/files/managed/07/b7/319433-023.pdfSigned-off-by Fenghua Yu <[email protected]>--- arch/x86/include/asm/cpufeature.h | 3 +++ 1 file changed, 3 insertions(+)arch/x86/include/asm/cpufeature.h +1
-0@@ -219,6 +219,7 @@#define X86_FEATURE_CQM ( 9*32+12)/* Cache QoS Monitoring */ #define X86_FEATURE_MPX ( 9*32+14)/* Memory Protection Extension */ #define X86_FEATURE_AVX512F ( 9*32+16)/* AVX-512 Foundation */ +#define X86_FEATURE_AVX512DQ ( 9*32+17)/* AVX-512 DQ Instructions */ #define X86_FEATURE_RDSEED ( 9*32+18)/* The RDSEED instruction */ #define X86_FEATURE_ADX ( 9*32+19)/* The ADCX and ADOX instructions */ #define X86_FEATURE_SMAP ( 9*32+20)/* Supervisor Mode Access Prevention */
arch/x86/include/asm/cpufeature.h line 237
Quoted 8 lines
arch/x86/include/asm/cpufeature.h +2
-0@@ -229,6 +230,8 @@#define X86_FEATURE_AVX512ER ( 9*32+27)/* AVX-512 Exponential and Reciprocal */ #define X86_FEATURE_AVX512CD ( 9*32+28)/* AVX-512 Conflict Detection */ #define X86_FEATURE_SHA_NI ( 9*32+29)/* SHA1/SHA256 Instruction Extensions */ +#define X86_FEATURE_AVX512BW ( 9*32+30)/* AVX-512 BW Instructions */ +#define X86_FEATURE_AVX512VL ( 9*32+31)/* AVX-512 Vector Lengths */ /* Extended state features, CPUID level 0x0000000d:1 (eax), word 10 */ #define X86_FEATURE_XSAVEOPT (10*32+ 0)/* XSAVEOPT */
In the latest x86 tree these defines are in cpufeatures.h, not cpufeature.h.
Thanks,
Ingo