Patch "EDAC, amd64_edac: Shift wrapping issue in f1x_get_norm_dct_addr()" has been added to the 3.14-stable tree

This is a note to let you know that I've just added the patch titled

EDAC, amd64_edac: Shift wrapping issue in f1x_get_norm_dct_addr()

to the 3.14-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
edac-amd64_edac-shift-wrapping-issue-in-f1x_get_norm_dct_addr.patch
and it can be found in the queue-3.14 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree, please let <[email protected]> know about it.

From: Dan Carpenter <[email protected]>
Date: Wed, 20 Jan 2016 12:54:51 +0300
Subject: EDAC, amd64_edac: Shift wrapping issue in f1x_get_norm_dct_addr()

From: Dan Carpenter <[email protected]>

commit 6f3508f61c814ee852c199988a62bd954c50dfc1 upstream.

dct_sel_base_off is declared as a u64 but we're only using the lower 32 bits because of a shift wrapping bug. This can possibly truncate the upper 16 bits of DctSelBaseOffset[47:26], causing us to misdecode the CS row.

---
 drivers/edac/amd64_edac.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

@@ -1294,7 +1294,7 @@ static u64 f1x_get_norm_dct_addr(struct
 	u64 chan_off;
 	u64 dram_base		= get_dram_base(pvt, range);
 	u64 hole_off		= f10_dhar_offset(pvt);
-	u64 dct_sel_base_off	= (pvt->dct_sel_hi & 0xFFFFFC00) << 16;
+	u64 dct_sel_base_off	= (u64)(pvt->dct_sel_hi & 0xFFFFFC00) << 16;
 
 	if (hi_rng) {
 		/*

Patches currently in stable-queue which might be from [email protected] are

queue-3.14/edac-amd64_edac-shift-wrapping-issue-in-f1x_get_norm_dct_addr.patch