Patch "clk: rockchip: rk3368: fix cpuclk core dividers" has been added to the 4.5-stable tree
Subsystems (3)
This is a note to let you know that I've just added the patch titled
clk: rockchip: rk3368: fix cpuclk core dividers
to the 4.5-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
clk-rockchip-rk3368-fix-cpuclk-core-dividers.patch
and it can be found in the queue-4.5 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree, please let <[email protected]> know about it.
Quoted 1 line
From
c6d5fe2ca8286f35a79f7345c9378c39d48a1527Mon Sep 17 00:00:00 2001
From: Heiko Stuebner <[email protected]>
Date: Tue, 19 Jan 2016 10:09:22 +0100
Subject: clk: rockchip: rk3368: fix cpuclk core dividers
From: Heiko Stuebner <[email protected]>
commit c6d5fe2ca8286f35a79f7345c9378c39d48a1527 upstream.
Similar to commit 9880d4277f6a ("clk: rockchip: fix rk3288 cpuclk core dividers") it seems the cpuclk dividers are one to high on the rk3368 as well.
And again similar to the previous fix, we opt to make the divider list contain the values to be written to use the same paradigm for them on all supported socs.
--- drivers/clk/rockchip/clk-rk3368.c | 40 +++++++++++++++++++------------------- 1 file changed, 20 insertions(+), 20 deletions(-)
drivers/clk/rockchip/clk-rk3368.c +20 -20
@@ -218,29 +218,29 @@ static const struct rockchip_cpuclk_reg_ }static struct rockchip_cpuclk_rate_table rk3368_cpuclkb_rates[]__initdata = { -RK3368_CPUCLKB_RATE (1512000000 ,2 ,6 ,6 ), -RK3368_CPUCLKB_RATE (1488000000 ,2 ,5 ,5 ), -RK3368_CPUCLKB_RATE (1416000000 ,2 ,5 ,5 ), -RK3368_CPUCLKB_RATE (1200000000 ,2 ,4 ,4 ), -RK3368_CPUCLKB_RATE (1008000000 ,2 ,4 ,4 ), -RK3368_CPUCLKB_RATE (816000000 ,2 ,3 ,3 ), -RK3368_CPUCLKB_RATE (696000000 ,2 ,3 ,3 ), -RK3368_CPUCLKB_RATE (600000000 ,2 ,2 ,2 ), -RK3368_CPUCLKB_RATE (408000000 ,2 ,2 ,2 ), -RK3368_CPUCLKB_RATE (312000000 ,2 ,2 ,2 ), +RK3368_CPUCLKB_RATE (1512000000 ,1 ,5 ,5 ), +RK3368_CPUCLKB_RATE (1488000000 ,1 ,4 ,4 ), +RK3368_CPUCLKB_RATE (1416000000 ,1 ,4 ,4 ), +RK3368_CPUCLKB_RATE (1200000000 ,1 ,3 ,3 ), +RK3368_CPUCLKB_RATE (1008000000 ,1 ,3 ,3 ), +RK3368_CPUCLKB_RATE (816000000 ,1 ,2 ,2 ), +RK3368_CPUCLKB_RATE (696000000 ,1 ,2 ,2 ), +RK3368_CPUCLKB_RATE (600000000 ,1 ,1 ,1 ), +RK3368_CPUCLKB_RATE (408000000 ,1 ,1 ,1 ), +RK3368_CPUCLKB_RATE (312000000 ,1 ,1 ,1 ), };static struct rockchip_cpuclk_rate_table rk3368_cpuclkl_rates[]__initdata = { -RK3368_CPUCLKL_RATE (1512000000 ,2 ,7 ,7 ), -RK3368_CPUCLKL_RATE (1488000000 ,2 ,6 ,6 ), -RK3368_CPUCLKL_RATE (1416000000 ,2 ,6 ,6 ), -RK3368_CPUCLKL_RATE (1200000000 ,2 ,5 ,5 ), -RK3368_CPUCLKL_RATE (1008000000 ,2 ,5 ,5 ), -RK3368_CPUCLKL_RATE (816000000 ,2 ,4 ,4 ), -RK3368_CPUCLKL_RATE (696000000 ,2 ,3 ,3 ), -RK3368_CPUCLKL_RATE (600000000 ,2 ,3 ,3 ), -RK3368_CPUCLKL_RATE (408000000 ,2 ,2 ,2 ), -RK3368_CPUCLKL_RATE (312000000 ,2 ,2 ,2 ), +RK3368_CPUCLKL_RATE (1512000000 ,1 ,6 ,6 ), +RK3368_CPUCLKL_RATE (1488000000 ,1 ,5 ,5 ), +RK3368_CPUCLKL_RATE (1416000000 ,1 ,5 ,5 ), +RK3368_CPUCLKL_RATE (1200000000 ,1 ,4 ,4 ), +RK3368_CPUCLKL_RATE (1008000000 ,1 ,4 ,4 ), +RK3368_CPUCLKL_RATE (816000000 ,1 ,3 ,3 ), +RK3368_CPUCLKL_RATE (696000000 ,1 ,2 ,2 ), +RK3368_CPUCLKL_RATE (600000000 ,1 ,2 ,2 ), +RK3368_CPUCLKL_RATE (408000000 ,1 ,1 ,1 ), +RK3368_CPUCLKL_RATE (312000000 ,1 ,1 ,1 ), };static struct rockchip_clk_branch rk3368_clk_branches[]__initdata = {
Patches currently in stable-queue which might be from [email protected] are
queue-4.5/clk-rockchip-rk3368-fix-cpuclk-core-dividers.patch queue-4.5/clk-rockchip-rk3368-fix-parents-of-video-encoder-decoder.patch queue-4.5/clk-rockchip-rk3368-fix-hdmi_cec-gate-register.patch queue-4.5/clk-rockchip-rk3368-fix-cpuclk-mux-bit-of-big-cpu-cluster.patch queue-4.5/clk-rockchip-add-hclk_cpubus-to-the-list-of-rk3188-critical-clocks.patch