Patch "MIPS: Fix MSA ld unaligned failure cases" has been added to the 4.4-stable tree
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This is a note to let you know that I've just added the patch titled
MIPS: Fix MSA ld unaligned failure cases
to the 4.4-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
mips-fix-msa-ld-unaligned-failure-cases.patch
and it can be found in the queue-4.4 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree, please let <[email protected]> know about it.
Quoted 1 line
From
fa8ff601d72bad3078ddf5ef17a5547700d06908Mon Sep 17 00:00:00 2001
From: Paul Burton <[email protected]>
Date: Wed, 3 Feb 2016 03:35:49 +0000
Subject: MIPS: Fix MSA ld unaligned failure cases
From: Paul Burton <[email protected]>
commit fa8ff601d72bad3078ddf5ef17a5547700d06908 upstream.
Copying the content of an MSA vector from user memory may involve TLB faults & mapping in pages. This will fail when preemption is disabled due to an inability to acquire mmap_sem from do_page_fault, which meant such vector loads to unmapped pages would always fail to be emulated. Fix this by disabling preemption later only around the updating of vector register state.
This change does however introduce a race between performing the load into thread context & the thread being preempted, saving its current live context & clobbering the loaded value. This should be a rare occureence, so optimise for the fast path by simply repeating the load if we are preempted.
Additionally if the copy failed then the failure path was taken with preemption left disabled, leading to the kernel typically encountering further issues around sleeping whilst atomic. The change to where preemption is disabled avoids this issue.
Patchwork: https://patchwork.linux-mips.org/patch/12345/
--- arch/mips/kernel/unaligned.c | 53 +++++++++++++++++++++++++------------------ 1 file changed, 31 insertions(+), 22 deletions(-)
arch/mips/kernel/unaligned.c +31 -22
@@ -885,7 +885,7 @@ static void emulate_load_store_insn(stru {union mips_instruction insn;unsigned long value; -unsigned int res; +unsigned int res, preempted;unsigned long origpc;unsigned long orig31;void __user *fault_addr =NULL ;
@@ -1226,27 +1226,36 @@ static void emulate_load_store_insn(struif (!access_ok (VERIFY_READ , addr,sizeof (*fpr))) goto sigbus; -/* -* Disable preemption to avoid a race between copying -* state from userland, migrating to another CPU and -* updating the hardware vector register below. -*/ -preempt_disable (); - - res =__copy_from_user_inatomic (fpr, addr, -sizeof (*fpr)); -if (res) - goto fault; - -/* -* Update the hardware register if it is in use by the -* task in this quantum, in order to avoid having to -* save & restore the whole vector context. -*/ -if (test_thread_flag (TIF_USEDMSA )) -write_msa_wr (wd, fpr, df); - -preempt_enable (); +do { +/* +* If we have live MSA context keep track of +* whether we get preempted in order to avoid +* the register context we load being clobbered +* by the live context as it's saved during +* preemption. If we don't have live context +* then it can't be saved to clobber the value +* we load. +*/ + preempted =test_thread_flag (TIF_USEDMSA ); + + res =__copy_from_user_inatomic (fpr, addr, +sizeof (*fpr)); +if (res) + goto fault; + +/* +* Update the hardware register if it is in use +* by the task in this quantum, in order to +* avoid having to save & restore the whole +* vector context. +*/ +preempt_disable (); +if (test_thread_flag (TIF_USEDMSA )) { +write_msa_wr (wd, fpr, df); + preempted =0 ; + } +preempt_enable (); + }while (preempted);break ;case msa_st_op:
Patches currently in stable-queue which might be from [email protected] are
queue-4.4/mips-fix-msa-ld-unaligned-failure-cases.patch