Patch "dmaengine: hsu: correct use of channel status register" has been added to the 4.4-stable tree

This is a note to let you know that I've just added the patch titled

dmaengine: hsu: correct use of channel status register

to the 4.4-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
dmaengine-hsu-correct-use-of-channel-status-register.patch
and it can be found in the queue-4.4 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree, please let <[email protected]> know about it.

From: Andy Shevchenko <[email protected]>
Date: Fri, 18 Mar 2016 14:26:32 +0200
Subject: dmaengine: hsu: correct use of channel status register

From: Andy Shevchenko <[email protected]>

commit 4f4bc0abff79dc9d7ccbd3143adbf8ad1f4fe6ab upstream.

There is a typo in documentation regarding to descriptor empty bit (DESCE) which is set to 1 when descriptor is empty. Thus, status register at the end of a transfer usually returns all DESCE bits set and thus it will never be zero.

Moreover, there are 2 bits (CDESC) that encode current descriptor, on which interrupt has been asserted. In case when we have few descriptors programmed we might have non-zero value.

Remove DESCE and CDESC bits from DMA channel status register (HSU_CH_SR) when reading it.

---
 drivers/dma/hsu/hsu.c |    2 +-
 drivers/dma/hsu/hsu.h |    3 +++
 2 files changed, 4 insertions(+), 1 deletion(-)

@@ -135,7 +135,7 @@ static u32 hsu_dma_chan_get_sr(struct hs
 	sr = hsu_chan_readl(hsuc, HSU_CH_SR);
 	spin_unlock_irqrestore(&hsuc->vchan.lock, flags);
 
-	return sr;
+	return sr & ~(HSU_CH_SR_DESCE_ANY | HSU_CH_SR_CDESC_ANY);
 }
 
 irqreturn_t hsu_dma_irq(struct hsu_dma_chip *chip, unsigned short nr)

@@ -41,6 +41,9 @@
 #define HSU_CH_SR_DESCTO(x)	BIT(8 + (x))
 #define HSU_CH_SR_DESCTO_ANY	(BIT(11) | BIT(10) | BIT(9) | BIT(8))
 #define HSU_CH_SR_CHE		BIT(15)
+#define HSU_CH_SR_DESCE(x)	BIT(16 + (x))
+#define HSU_CH_SR_DESCE_ANY	(BIT(19) | BIT(18) | BIT(17) | BIT(16))
+#define HSU_CH_SR_CDESC_ANY	(BIT(31) | BIT(30))
 
 /* Bits in HSU_CH_CR */
 #define HSU_CH_CR_CHA		BIT(0)

Patches currently in stable-queue which might be from [email protected] are

queue-4.4/dmaengine-hsu-correct-use-of-channel-status-register.patch queue-4.4/dmaengine-dw-fix-master-selection.patch