Skip to contentSkip to conversation

Patch "clk: qcom: msm8960: fix ce3_core clk enable register" has been added to the 4.4-stable tree

PATCH [email protected] 1 participant 1 message May 6, 2016

Subsystems (4)
lore
Share & tools
lore

[email protected]

author maintainer Applied
#0 lore raw

This is a note to let you know that I've just added the patch titled

clk: qcom: msm8960: fix ce3_core clk enable register

to the 4.4-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:

     clk-qcom-msm8960-fix-ce3_core-clk-enable-register.patch

and it can be found in the queue-4.4 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree, please let <[email protected]> know about it.

Quoted 1 line

From 732d6913691848db9fabaa6a25b4d6fad10ddccf Mon Sep 17 00:00:00 2001

From: Srinivas Kandagatla <[email protected]>
Date: Mon, 22 Feb 2016 11:43:39 +0000
Subject: clk: qcom: msm8960: fix ce3_core clk enable register

From: Srinivas Kandagatla <[email protected]>

commit 732d6913691848db9fabaa6a25b4d6fad10ddccf upstream.

This patch corrects the enable register offset which is actually 0x36cc instead of 0x36c4

Fixes 5f775498bdc4 ("clk: qcom: Fully support apq8064 global clock control")
---
 drivers/clk/qcom/gcc-msm8960.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/clk/qcom/gcc-msm8960.c +1 -1
@@ -2769,7 +2769,7 @@ static struct clk_branch ce3_core_clk =
 	.halt_reg = 0x2fdc,
 	.halt_bit = 5,
 	.clkr = {
-		.enable_reg = 0x36c4,
+		.enable_reg = 0x36cc,
 		.enable_mask = BIT(4),
 		.hw.init = &(struct clk_init_data){
 			.name = "ce3_core_clk",

Patches currently in stable-queue which might be from [email protected] are

queue-4.4/clk-qcom-msm8960-fix-ce3_src-register-offset.patch queue-4.4/clk-qcom-msm8960-fix-ce3_core-clk-enable-register.patch