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Patch "ARC: Add missing io barriers to io{read,write}{16,32}be()" has been added to the 4.5-stable tree

PATCH [email protected] 1 participant 1 message May 8, 2016

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This is a note to let you know that I've just added the patch titled

ARC: Add missing io barriers to io{read,write}{16,32}be()

to the 4.5-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:

     arc-add-missing-io-barriers-to-io-read-write-16-32-be.patch

and it can be found in the queue-4.5 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree, please let <[email protected]> know about it.

Quoted 1 line

From e5bc0478ab6cf565619224536d75ecb2aedca43b Mon Sep 17 00:00:00 2001

From: Vineet Gupta <[email protected]>
Date: Thu, 5 May 2016 13:32:34 +0530
Subject: ARC: Add missing io barriers to io{read,write}{16,32}be()

From: Vineet Gupta <[email protected]>

commit e5bc0478ab6cf565619224536d75ecb2aedca43b upstream.

While reviewing a different change to asm-generic/io.h Arnd spotted that ARC ioread32 and ioread32be both of which come from asm-generic versions are not symmetrical in terms of calling the io barriers.

generic ioread32 -> ARC readl() [ has barriers]
generic ioread32be -> __be32_to_cpu(__raw_readl()) [ lacks barriers]

While generic ioread32be is being remediated to call readl(), that involves a swab32(), causing double swaps on ioread32be() on Big Endian systems.

So provide our versions of big endian IO accessors to ensure io barrier calls while also keeping them optimal

Suggested-by Arnd Bergmann <[email protected]>
Acked-by Arnd Bergmann <[email protected]>
Signed-off-by Vineet Gupta <[email protected]>
Signed-off-by Greg Kroah-Hartman <[email protected]>
---
 arch/arc/include/asm/io.h |   27 ++++++++++++++++++---------
 1 file changed, 18 insertions(+), 9 deletions(-)
arch/arc/include/asm/io.h +18 -9
@@ -13,6 +13,15 @@
 #include <asm/byteorder.h>
 #include <asm/page.h>
 
+#ifdef CONFIG_ISA_ARCV2
+#include <asm/barrier.h>
+#define __iormb()		rmb()
+#define __iowmb()		wmb()
+#else
+#define __iormb()		do { } while (0)
+#define __iowmb()		do { } while (0)
+#endif
+
 extern void __iomem *ioremap(unsigned long physaddr, unsigned long size);
 extern void __iomem *ioremap_prot(phys_addr_t offset, unsigned long size,
 				  unsigned long flags);

@@ -22,6 +31,15 @@ extern void iounmap(const void __iomem *
 #define ioremap_wc(phy, sz)		ioremap(phy, sz)
 #define ioremap_wt(phy, sz)		ioremap(phy, sz)
 
+/*
+ * io{read,write}{16,32}be() macros
+ */
+#define ioread16be(p)		({ u16 __v = be16_to_cpu((__force __be16)__raw_readw(p)); __iormb(); __v; })
+#define ioread32be(p)		({ u32 __v = be32_to_cpu((__force __be32)__raw_readl(p)); __iormb(); __v; })
+
+#define iowrite16be(v,p)	({ __iowmb(); __raw_writew((__force u16)cpu_to_be16(v), p); })
+#define iowrite32be(v,p)	({ __iowmb(); __raw_writel((__force u32)cpu_to_be32(v), p); })
+
 /* Change struct page to physical address */
 #define page_to_phys(page)		(page_to_pfn(page) << PAGE_SHIFT)
 

@@ -99,15 +117,6 @@ static inline void __raw_writel(u32 w, v
 
 }
 
-#ifdef CONFIG_ISA_ARCV2
-#include <asm/barrier.h>
-#define __iormb()		rmb()
-#define __iowmb()		wmb()
-#else
-#define __iormb()		do { } while (0)
-#define __iowmb()		do { } while (0)
-#endif
-
 /*
  * MMIO can also get buffered/optimized in micro-arch, so barriers needed
  * Based on ARM model for the typical use case

Patches currently in stable-queue which might be from [email protected] are

queue-4.5/arc-add-missing-io-barriers-to-io-read-write-16-32-be.patch