dt: bindings: spi-bcm-qspi: NSP, NS2, BRCMSTB SoC bindings
PATCH 1/4 dt: bindings: spi-bcm-qspi: NSP, NS2, BRCMSTB SoC bindings
Added device tree bindings documentation for SoCs supported by the new spi-bcm-qspi driver.
Signed-off-by Kamal Dasu <[email protected]>
--- .../devicetree/bindings/spi/spi-bcm-qspi.txt | 228 +++++++++++++++++++++ 1 file changed, 228 insertions(+) create mode 100644 Documentation/devicetree/bindings/spi/spi-bcm-qspi.txt
Documentation/devicetree/bindings/spi/spi-bcm-qspi.txt new file +228 -0
@@ -0,0 +1,228 @@ +Broadcom SPI controller + +The Broadcom SPI controller is a SPI master found on various SOCs, including +BRCMSTB (BCM7XXX), Cygnus, NSP and NS2. + +Required properties: + +- #address-cells: + Must be <1>, as required by generic SPI binding. + +- #size-cells: + Must be <0>, also as required by generic SPI binding. + +- compatible: + Must be one of : + "brcm,spi-bcm-qspi" + "brcm,spi-brmstb" spi-nor and/or "brcm,spi-brmstb-mspi" unmanaged SPI Master + +- reg: + Define the bases and ranges of the associated I/O address spaces. + The required range is MSPI controller registers and interrupt registers, the others + are optional Boot SPI (BSPI) portion for fast flash reads. + +- reg-names: + First name does not matter, but must be reserved for the MSPI controller + register range as mentioned in 'reg' above, and will typically contain + - "bspi_regs": BSPI register range + - "mspi_regs": MSPI register range + - "intr_regs", "intr_status_reg" : Interrupt and status register for NSP, NS2 SoC + - "hif_spi_intr2" : Interrupt and status register for BRCMSTB SoC + +- interrupts + The interrupts used by the MSPI and/or BSPI controller. + +- interrupt-names: + Names of interrupts associated with this MSPI and/or BSPI controller. + - "mspi_halted" : + - "mspi_done": Indicates that the requested SPI operation is complete. + - "spi_lr_fullness_reached" : Linear read BSPI pipe full + - "spi_lr_session_aborted" : Linear read BSPI pipe aborted + - "spi_lr_impatient" : Linear read BSPI requested when pipe empty + - "spi_lr_session_done" : Linear read BSPI session done + +Optional properties: + +- clocks: + A phandle to the reference clock for this block. If not present, will + assume a 27 MHz fixed clock (default for UPG). + + +Optional properties: + +- clocks: + A phandle to the reference clock for this block. + +- bspi-sel: + Chip selects that requires bspi support. + + +Examples: + +BRCMSTB SoC Example: + + SPI Master for SPI-NOR: + + spi@f03e3400 { + #address-cells = <0x1>; + #size-cells = <0x0>; + compatible = "brcm,qspi-brcmstb"; + reg = <0xf03e0920 0x4 0xf03e3400 0x188 0xf03e3200 0x50>; + reg-names = "cs_reg", "hif_mspi", "bspi"; + interrupts = <0x6 0x5 0x4 0x3 0x2 0x1 0x0>; + interrupt-parent = <0x1c>; + interrupt-names = "mspi_halted", + "mspi_done", + "spi_lr_overread", + "spi_lr_session_done", + "spi_lr_impatient", + "spi_lr_session_aborted", + "spi_lr_fullness_reached"; + + clocks = <0x1b>; + clock-names = "sw_spi"; + + m25p80@0 { + #size-cells = <0x2>; + #address-cells = <0x2>; + compatible = "m25p80"; + reg = <0x0>; + spi-max-frequency = <0x2625a00>; + spi-cpol; + spi-cpha; + use-bspi; + m25p,fast-read; + + flash0.bolt@0 { + reg = <0x0 0x0 0x0 0x100000>; + }; + + flash0.macadr@100000 { + reg = <0x0 0x100000 0x0 0x10000>; + }; + + flash0.nvram@110000 { + reg = <0x0 0x110000 0x0 0x10000>; + }; + + flash0.kernel@120000 { + reg = <0x0 0x120000 0x0 0x400000>; + }; + + flash0.devtree@520000 { + reg = <0x0 0x520000 0x0 0x10000>; + }; + + flash0.splash@530000 { + reg = <0x0 0x530000 0x0 0x80000>; + }; + + flash0@0 { + reg = <0x0 0x0 0x0 0x4000000>; + }; + }; + }; + + + MSPI master: + + spi@f0416000 { + #address-cells = <1>; + #size-cells = <0>; + clocks = <&upg_fixed>; + compatible = "brcm,spi-brcmstb-mspi"; + reg = <0xf0416000 0x180>; + reg-names = "mspi"; + interrupts = <0x14>; + interrupt-parent = <&irq0_aon_intc>; + interrupt-names = "mspi_done"; + }; + + + +iProc SoC Example: + + qspi: spi@18027200 { + compatible = "brcm,spi-bcm-qspi"; + reg = <0x18027200 0x184>, + <0x18027000 0x124>, + <0x1811c408 0x004>, + <0x180273a0 0x01c>; + reg-names = "mspi_regs", "bspi_regs", "intr_regs", "intr_status_reg"; + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = + "spi_lr_fullness_reached", + "spi_lr_session_aborted", + "spi_lr_impatient", + "spi_lr_session_done", + "mspi_done", + "mspi_halted"; + clocks = <&iprocmed>; + clock-names = "iprocmed"; + clock-frequency = <12500000>; + num-cs = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + + + NS2 SoC Example: + + qspi: spi@66470200 { + compatible = "brcm,spi-bcm-qspi"; + reg = <0x66470200 0x184>, + <0x66470000 0x124>, + <0x67017408 0x004>, + <0x664703a0 0x01c>; + reg-names = "mspi", "bspi", "intr_regs", "intr_status_reg"; + interrupts = <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "spi_l1_intr"; + clocks = <&iprocmed>; + clock-names = "iprocmed"; + clock-frequency = <12500000>; + num-cs = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + + + m25p80 node for NSP, NS2 and iProc + + &qspi { + bspi-sel = <0>; + flash: m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "m25p80"; + reg = <0x0>; + spi-max-frequency = <12500000>; + m25p,fast-read; + spi-cpol; + spi-cpha; + + partition@0 { + label = "boot"; + reg = <0x00000000 0x000a0000>; + }; + + partition@1 { + label = "env"; + reg = <0x000a0000 0x00060000>; + }; + + partition@2 { + label = "system"; + reg = <0x00100000 0x00600000>; + }; + + partition@3 { + label = "rootfs"; + reg = <0x00700000 0x01900000>; + }; + };
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PATCH 2/4 spi: bcm-qspi: Add SPI flash and MSPI driver
Adding unified SPI flash and MSPI driver for Broadcom BRCMSTB, NS2, NSP SoCs. Driver shall work with brcm,7120-l2-intc or brcm-l2-intc or with a single muxed L1 interrupt source.
Signed-off-by Kamal Dasu <[email protected]>
--- drivers/spi/Kconfig | 6 + drivers/spi/Makefile | 1 + drivers/spi/spi-bcm-qspi.c | 1807 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 1814 insertions(+) create mode 100644 drivers/spi/spi-bcm-qspi.c
drivers/spi/Kconfig +6 -0
@@ -153,6 +153,12 @@ config SPI_BCM63XX_HSSPI This enables support for the High Speed SPI controller present on newer Broadcom BCM63XX SoCs. +config SPI_BCM_QSPI + tristate "Broadcom BSPI and MSPI controller support" + help + Enables support for the Broadcom SPI flash and MSPI controller. + Currently supports BRCMSTB, NSP, NS2 SoCs + config SPI_BITBANG tristate "Utilities for Bitbanging SPI masters" help
drivers/spi/Makefile +1 -0
@@ -21,6 +21,7 @@ obj-$(CONFIG_SPI_BCM2835AUX) += spi-bcm2835aux.o obj-$(CONFIG_SPI_BCM53XX) += spi-bcm53xx.o obj-$(CONFIG_SPI_BCM63XX) += spi-bcm63xx.o obj-$(CONFIG_SPI_BCM63XX_HSSPI) += spi-bcm63xx-hsspi.o +obj-$(CONFIG_SPI_BCM_QSPI) += spi-bcm-qspi.o obj-$(CONFIG_SPI_BFIN5XX) += spi-bfin5xx.o obj-$(CONFIG_SPI_ADI_V3) += spi-adi-v3.o obj-$(CONFIG_SPI_BFIN_SPORT) += spi-bfin-sport.o
drivers/spi/spi-bcm-qspi.c new file +1807 -0
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PATCH 3/4 arm: dts: Add bcm-nsp and bcm958625k support
In reply to a message not in the archiveAdding qspi node compatible with the new spi-bcm-qspi driver for the broadcom's northstar SoCwq.
Signed-off-by Kamal Dasu <[email protected]>
--- arch/arm/boot/dts/bcm-nsp.dtsi | 29 +++++++++++++++++++++++++++++ arch/arm/boot/dts/bcm958625k.dts | 34 ++++++++++++++++++++++++++++++++++ 2 files changed, 63 insertions(+)
arch/arm/boot/dts/bcm-nsp.dtsi +29 -0
@@ -206,6 +206,35 @@ brcm,nand-has-wp; }; + qspi: qspi@27200 { + compatible = "brcm,spi-bcm-qspi"; + reg = <0x027200 0x184>, + <0x027000 0x124>, + <0x11c408 0x004>, + <0x0273a0 0x01c>; + reg-names = "mspi", "bspi", "intr_regs", "intr_status_reg"; + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "spi_lr_fullness_reached", + "spi_lr_session_aborted", + "spi_lr_impatient", + "spi_lr_session_done", + "spi_lr_overhead", + "mspi_done", + "mspi_halted"; + clocks = <&iprocmed>; + clock-names = "iprocmed"; + clock-frequency = <12500000>; + num-cs = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + ccbtimer0: timer@34000 { compatible = "arm,sp804"; reg = <0x34000 0x1000>;
arch/arm/boot/dts/bcm958625k.dts +34 -0
@@ -114,3 +114,37 @@ groups = "nand_grp"; }; }; + +&qspi { + bspi-sel = <0>; + flash: m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "m25p80"; + reg = <0x0>; + spi-max-frequency = <12500000>; + m25p,fast-read; + spi-cpol; + spi-cpha; + + partition@0 { + label = "boot"; + reg = <0x00000000 0x000a0000>; + }; + + partition@1 { + label = "env"; + reg = <0x000a0000 0x00060000>; + }; + + partition@2 { + label = "system"; + reg = <0x00100000 0x00600000>; + }; + + partition@3 { + label = "rootfs"; + reg = <0x00700000 0x01900000>; + }; + }; +};
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PATCH 4/4 arm64: dts: Add ns2 SoC support
In reply to a message not in the archiveAdding qspi node compatible with the new spi-bcm-qspi driver for the broadcom's northstar2 SoC.
Signed-off-by Kamal Dasu <[email protected]>
--- arch/arm64/boot/dts/broadcom/ns2-svk.dts | 34 ++++++++++++++++++++++++++++++++ arch/arm64/boot/dts/broadcom/ns2.dtsi | 18 +++++++++++++++++ 2 files changed, 52 insertions(+)
arch/arm64/boot/dts/broadcom/ns2-svk.dts +34 -0
@@ -87,3 +87,37 @@ #size-cells = <1>; }; }; + +&qspi { + bspi-sel = <0>; + flash: m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "m25p80"; + reg = <0x0>; + spi-max-frequency = <12500000>; + m25p,fast-read; + spi-cpol; + spi-cpha; + + partition@0 { + label = "boot"; + reg = <0x00000000 0x000a0000>; + }; + + partition@1 { + label = "env"; + reg = <0x000a0000 0x00060000>; + }; + + partition@2 { + label = "system"; + reg = <0x00100000 0x00600000>; + }; + + partition@3 { + label = "rootfs"; + reg = <0x00700000 0x01900000>; + }; + }; +};
arch/arm64/boot/dts/broadcom/ns2.dtsi +18 -0
@@ -444,5 +444,23 @@ brcm,nand-has-wp; }; + + qspi: spi@66470200 { + compatible = "brcm,spi-bcm-qspi"; + reg = <0x66470200 0x184>, + <0x66470000 0x124>, + <0x67017408 0x004>, + <0x664703a0 0x01c>; + reg-names = "mspi", "bspi", "intr_regs", "intr_status_reg"; + interrupts = <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "spi_l1_intr"; + clocks = <&iprocmed>; + clock-names = "iprocmed"; + clock-frequency = <12500000>; + num-cs = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; };
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