Patch "clk: bcm2835: divider value has to be 1 or more" has been added to the 4.5-stable tree

This is a note to let you know that I've just added the patch titled

clk: bcm2835: divider value has to be 1 or more

to the 4.5-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:

     clk-bcm2835-divider-value-has-to-be-1-or-more.patch

and it can be found in the queue-4.5 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree, please let <[email protected]> know about it.

From: Martin Sperl <[email protected]>
Date: Mon, 29 Feb 2016 11:39:20 +0000
Subject: clk: bcm2835: divider value has to be 1 or more

From: Martin Sperl <[email protected]>

commit 997f16bd5d2e9b3456027f96fcadfe1e2bf12f4e upstream.

Current clamping of a normal divider allows a value < 1 to be valid.

A divider of < 1 would actually only be possible if we had a PLL...

So this patch clamps the divider to 1.

audio domain clocks")

---
 drivers/clk/bcm/clk-bcm2835.c |    5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

@@ -1193,8 +1193,9 @@ static u32 bcm2835_clock_choose_div(stru
 		div += unused_frac_mask + 1;
 	div &= ~unused_frac_mask;
 
-	/* Clamp to the limits. */
-	div = max(div, unused_frac_mask + 1);
+	/* clamp to min divider of 1 */
+	div = max_t(u32, div, 1 << CM_DIV_FRAC_BITS);
+	/* clamp to the highest possible fractional divider */
 	div = min_t(u32, div, GENMASK(data->int_bits + CM_DIV_FRAC_BITS - 1,
 				      CM_DIV_FRAC_BITS - data->frac_bits));
 

Patches currently in stable-queue which might be from [email protected] are

queue-4.5/clk-bcm2835-correctly-enable-fractional-clock-support.patch queue-4.5/clk-bcm2835-pll_off-should-only-update-cm_pll_anarst.patch queue-4.5/clk-bcm2835-divider-value-has-to-be-1-or-more.patch