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ppc: Properly tag the translation cache based on MMU mode

PATCH In review Benjamin Herrenschmidt 4 participants 4 messages Jun 6, 2016 – Jun 7, 2016

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Benjamin Herrenschmidt

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#0 lore raw

PATCH 1/2 ppc: Properly tag the translation cache based on MMU mode

We used to always flush the TLB when changing relocation mode in MSR:IR and MSR:DR (ie. MMU on/off for Instructions and Data).

We don't anymore since we have split mmu_idx for instruction and data.

However, since we hard code the mmu_idx in the translated code, we now need to also make sure MSR:IR and MSR:DR are part of the hflags used to tag translated code, so that we use different translated code for different MMU settings.

Darwin gets hurt by this problem.

Signed-off-by Benjamin Herrenschmidt <[email protected]>

---
 target-ppc/helper_regs.h | 2 +-

 1 file changed, 1 insertion(+), 1 deletion(-)
target-ppc/helper_regs.h +0 -0
index 12af61c..104b690 100644
@@ -95,7 +95,7 @@ static inline void hreg_compute_hflags(CPUPPCState *env)

     /* We 'forget' FE0 & FE1: we'll never generate imprecise exceptions */ hflags_mask = (1 << MSR_VR) | (1 << MSR_AP) | (1 << MSR_SA) | (1 << MSR_PR) | (1 << MSR_FP) | (1 << MSR_SE) | (1 << MSR_BE) | -        (1 << MSR_LE) | (1 << MSR_VSX);
+        (1 << MSR_LE) | (1 << MSR_VSX) | (1 << MSR_IR) | (1 << MSR_DR); hflags_mask |= (1ULL << MSR_CM) | (1ULL << MSR_SF) | MSR_HVB; hreg_compute_mem_idx(env);
     env->hflags = env->msr & hflags_mask;

Tested-by on v1 1/2
#1 lore raw
Quoted 5 lines · Benjamin Herrenschmidt

We used to always flush the TLB when changing relocation mode in MSR:IR and MSR:DR (ie. MMU on/off for Instructions and Data).

We don't anymore since we have split mmu_idx for instruction and data.

Quoted 8 lines

However, since we hard code the mmu_idx in the translated code, we now need to also make sure MSR:IR and MSR:DR are part of the hflags used to tag translated code, so that we use different translated code for different MMU settings.

Darwin gets hurt by this problem.

Signed-off-by Benjamin Herrenschmidt <[email protected]>

Looks good on G3 and G4 running macosx10.2 and macosx10.4.

Tested-by Cédric Le Goater <[email protected]>
Quoted 19 lines
---
 target-ppc/helper_regs.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
target-ppc/helper_regs.h +1 -1
index 12af61c..104b690 100644
@@ -95,7 +95,7 @@ static inline void hreg_compute_hflags(CPUPPCState *env)
     /* We 'forget' FE0 & FE1: we'll never generate imprecise exceptions */
     hflags_mask = (1 << MSR_VR) | (1 << MSR_AP) | (1 << MSR_SA) |
         (1 << MSR_PR) | (1 << MSR_FP) | (1 << MSR_SE) | (1 << MSR_BE) |
-        (1 << MSR_LE) | (1 << MSR_VSX);
+        (1 << MSR_LE) | (1 << MSR_VSX) | (1 << MSR_IR) | (1 << MSR_DR);
     hflags_mask |= (1ULL << MSR_CM) | (1ULL << MSR_SF) | MSR_HVB;
     hreg_compute_mem_idx(env);
     env->hflags = env->msr & hflags_mask;
Tested-by on v1 1/2
#2 lore raw
In reply to Benjamin Herrenschmidt
Quoted 25 lines · Benjamin Herrenschmidt

We used to always flush the TLB when changing relocation mode in MSR:IR and MSR:DR (ie. MMU on/off for Instructions and Data).

We don't anymore since we have split mmu_idx for instruction and data.

However, since we hard code the mmu_idx in the translated code, we now need to also make sure MSR:IR and MSR:DR are part of the hflags used to tag translated code, so that we use different translated code for different MMU settings.

Darwin gets hurt by this problem.

Signed-off-by Benjamin Herrenschmidt <[email protected]>
---
 target-ppc/helper_regs.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
target-ppc/helper_regs.h +0 -0
index 12af61c..104b690 100644

target-ppc/helper_regs.h static inline void hreg_compute_hflags(CPUPPCState *env) · line 101

Quoted 8 lines
target-ppc/helper_regs.h +1 -1
@@ -95,7 +95,7 @@ static inline void hreg_compute_hflags(CPUPPCState *env)
     /* We 'forget' FE0 & FE1: we'll never generate imprecise exceptions */
     hflags_mask = (1 << MSR_VR) | (1 << MSR_AP) | (1 << MSR_SA) |
         (1 << MSR_PR) | (1 << MSR_FP) | (1 << MSR_SE) | (1 << MSR_BE) |
-        (1 << MSR_LE) | (1 << MSR_VSX);
+        (1 << MSR_LE) | (1 << MSR_VSX) | (1 << MSR_IR) | (1 << MSR_DR);
     hflags_mask |= (1ULL << MSR_CM) | (1ULL << MSR_SF) | MSR_HVB;
     hreg_compute_mem_idx(env);
     env->hflags = env->msr & hflags_mask;

I've run through my complete set of OpenBIOS boot tests with both this and patch 2 applied on top of Cédric's recent fixes and I no longer see any regressions with g3beige/mac99 under TCG:

Tested-by Mark Cave-Ayland <[email protected]>

ATB,

Mark.

#3 lore raw
In reply to Benjamin Herrenschmidt
Quoted 5 lines · Benjamin Herrenschmidt

We used to always flush the TLB when changing relocation mode in MSR:IR and MSR:DR (ie. MMU on/off for Instructions and Data).

We don't anymore since we have split mmu_idx for instruction and data.

Quoted 8 lines

However, since we hard code the mmu_idx in the translated code, we now need to also make sure MSR:IR and MSR:DR are part of the hflags used to tag translated code, so that we use different translated code for different MMU settings.

Darwin gets hurt by this problem.

Signed-off-by Benjamin Herrenschmidt <[email protected]>

Bizarrely, patch complained about a malformed diff on this one for reasons I couldn't figure out. I recreated manually and applied to ppc-for-2.7.

Quoted 19 lines

---
 target-ppc/helper_regs.h | 2 +-

 1 file changed, 1 insertion(+), 1 deletion(-)
target-ppc/helper_regs.h +0 -0
index 12af61c..104b690 100644
@@ -95,7 +95,7 @@ static inline void hreg_compute_hflags(CPUPPCState *env)
      /* We 'forget' FE0 & FE1: we'll never generate imprecise exceptions */

     hflags_mask = (1 << MSR_VR) | (1 << MSR_AP) | (1 << MSR_SA) | (1 << MSR_PR) | (1 << MSR_FP) | (1 << MSR_SE) | (1 << MSR_BE) | -        (1 << MSR_LE) | (1 << MSR_VSX);
+        (1 << MSR_LE) | (1 << MSR_VSX) | (1 << MSR_IR) | (1 << MSR_DR); hflags_mask |= (1ULL << MSR_CM) | (1ULL << MSR_SF) | MSR_HVB; hreg_compute_mem_idx(env);
     env->hflags = env->msr & hflags_mask;

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