Patch "drm/nouveau/disp/sor/gf119: both links use the same training register" has been added to the 4.6-stable tree
Subsystems (4)
This is a note to let you know that I've just added the patch titled
drm/nouveau/disp/sor/gf119: both links use the same training register
to the 4.6-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
drm-nouveau-disp-sor-gf119-both-links-use-the-same-training-register.patch
and it can be found in the queue-4.6 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree, please let <[email protected]> know about it.
Quoted 1 line
From
a8953c52b95167b5d21a66f0859751570271d834Mon Sep 17 00:00:00 2001
From: Ben Skeggs <[email protected]>
Date: Fri, 3 Jun 2016 14:37:40 +1000
Subject: drm/nouveau/disp/sor/gf119: both links use the same training register
From: Ben Skeggs <[email protected]>
commit a8953c52b95167b5d21a66f0859751570271d834 upstream.
It appears that, for whatever reason, both link A and B use the same register to control the training pattern. It's a little odd, as the GPUs before this (Tesla/Fermi1) have per-link registers, as do newer GPUs (Maxwell).
Fixes the third DP output on NVS 510 (GK107).
--- drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf119.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-)
drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf119.c +1 -2
@@ -40,8 +40,7 @@ static int gf119_sor_dp_pattern(struct nvkm_output_dp *outp, int pattern) {struct nvkm_device *device = outp->base.disp->engine.subdev.device; -const u32 loff =gf119_sor_loff (outp); -nvkm_mask (device,0x61c110 + loff,0x0f0f0f0f ,0x01010101 * pattern); +nvkm_mask (device,0x61c110 ,0x0f0f0f0f ,0x01010101 * pattern);return 0 ; }
Patches currently in stable-queue which might be from [email protected] are
queue-4.6/drm-nouveau-fix-for-disabled-fbdev-emulation.patch queue-4.6/drm-nouveau-disp-sor-gf119-both-links-use-the-same-training-register.patch queue-4.6/drm-nouveau-gr-gf100-update-sm-error-decoding-from-gk20a-nvgpu-headers.patch queue-4.6/drm-nouveau-revert-drm-nouveau-device-pci-set-as-non-cpu-coherent-on-arm64.patch queue-4.6/drm-nouveau-bios-disp-fix-handling-of-match-any-protocol-entries.patch queue-4.6/drm-nouveau-disp-sor-gf119-select-correct-sor-when-poking-training-pattern.patch queue-4.6/drm-nouveau-disp-sor-gm107-training-pattern-registers-are-like-gm200.patch queue-4.6/drm-nouveau-fbcon-fix-out-of-bounds-memory-accesses.patch queue-4.6/drm-nouveau-ltc-gm107-fix-typo-in-the-address-of-nv_pltcg_ltc0_lts0_intr.patch