Patch "clk: rockchip: fix incorrect rk3399 spdif-DPTX divider bits" has been added to the 4.7-stable tree

This is a note to let you know that I've just added the patch titled

clk: rockchip: fix incorrect rk3399 spdif-DPTX divider bits

to the 4.7-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
clk-rockchip-fix-incorrect-rk3399-spdif-dptx-divider-bits.patch
and it can be found in the queue-4.7 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree, please let <[email protected]> know about it.

From: Xing Zheng <[email protected]>
Date: Thu, 30 Jun 2016 10:18:59 +0800
Subject: clk: rockchip: fix incorrect rk3399 spdif-DPTX divider bits

From: Xing Zheng <[email protected]>

commit 3770821fa360525e6c726cd562a2438a0aa5d566 upstream.

The CLKSEL_CON32 bit_0 is controlled for spdif_8ch, not spdif_rec_dptx, it should be bit_8, let's fix it.

---
 drivers/clk/rockchip/clk-rk3399.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

@@ -586,7 +586,7 @@ static struct rockchip_clk_branch rk3399
 			RK3399_CLKGATE_CON(8), 15, GFLAGS),
 
 	COMPOSITE(SCLK_SPDIF_REC_DPTX, "clk_spdif_rec_dptx", mux_pll_src_cpll_gpll_p, 0,
-			RK3399_CLKSEL_CON(32), 15, 1, MFLAGS, 0, 5, DFLAGS,
+			RK3399_CLKSEL_CON(32), 15, 1, MFLAGS, 8, 5, DFLAGS,
 			RK3399_CLKGATE_CON(10), 6, GFLAGS),
 	/* i2s */
 	COMPOSITE(0, "clk_i2s0_div", mux_pll_src_cpll_gpll_p, 0,

Patches currently in stable-queue which might be from [email protected] are

queue-4.7/clk-rockchip-fix-incorrect-rk3399-spdif-dptx-divider-bits.patch