Patch "drm/i915: Update CDCLK_FREQ register on BDW after changing cdclk frequency" has been added to the 4.7-stable tree

This is a note to let you know that I've just added the patch titled

drm/i915: Update CDCLK_FREQ register on BDW after changing cdclk frequency

to the 4.7-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
drm-i915-update-cdclk_freq-register-on-bdw-after-changing-cdclk-frequency.patch
and it can be found in the queue-4.7 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree, please let <[email protected]> know about it.

From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <[email protected]>
Date: Tue, 26 Apr 2016 19:46:32 +0300
Subject: drm/i915: Update CDCLK_FREQ register on BDW after changing cdclk frequency
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From: Ville Syrjälä <[email protected]>

commit 7f1052a8fa38df635ab0dc0e6025b64ab9834824 upstream.

Update CDCLK_FREQ on BDW after changing the cdclk frequency. Not sure if this is a late addition to the spec, or if I simply overlooked this step when writing the original code.

This is what Bspec has to say about CDCLK_FREQ:
"Program this field to the CD clock frequency minus one. This is used to
generate a divided down clock for miscellaneous timers in display."

And the "Broadwell Sequences for Changing CD Clock Frequency" section clarifies this further:
"For CD clock 337.5 MHz, program 337 decimal.
For CD clock 450 MHz, program 449 decimal.
For CD clock 540 MHz, program 539 decimal.
For CD clock 675 MHz, program 674 decimal."

---
 drivers/gpu/drm/i915/i915_reg.h      |    2 ++
 drivers/gpu/drm/i915/intel_display.c |    2 ++
 2 files changed, 4 insertions(+)

@@ -7538,6 +7538,8 @@ enum skl_disp_power_wells {
 
 #define CDCLK_FREQ			_MMIO(0x46200)
 
+#define CDCLK_FREQ			_MMIO(0x46200)
+
 #define _TRANSA_MSA_MISC		0x60410
 #define _TRANSB_MSA_MISC		0x61410
 #define _TRANSC_MSA_MISC		0x62410

@@ -9700,6 +9700,8 @@ static void broadwell_set_cdclk(struct d
 
 	I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
 
+	I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
+
 	intel_update_cdclk(dev);
 
 	WARN(cdclk != dev_priv->cdclk_freq,

Patches currently in stable-queue which might be from [email protected] are

queue-4.7/drm-edid-add-6-bpc-quirk-for-display-aeo-model-0.patch queue-4.7/drm-aux-transfer-can-return-0-deal-with-it.patch queue-4.7/drm-i915-update-cdclk_freq-register-on-bdw-after-changing-cdclk-frequency.patch