Introducing the FSI device driver

From: Chris Bostic <[email protected]>

Define the FSI master control register set and its accessors. Initialize the primary FSI master.

Signed-off-by Chris Bostic <[email protected]>

---

 drivers/fsi/Makefile      |   2 +-
 drivers/fsi/fsi.h         |  32 +++
 drivers/fsi/fsi_private.h |  97 +++++++
 drivers/fsi/fsicfam.h     |  46 ++++
 drivers/fsi/fsiinit.c     |  22 ++
 drivers/fsi/fsiinit.h     |   2 +
 drivers/fsi/fsimaster.c   | 242 +++++++++++++++++
 drivers/fsi/fsimaster.h   | 655 ++++++++++++++++++++++++++++++++++++++++++++++
 8 files changed, 1097 insertions(+), 1 deletion(-)
 create mode 100644 drivers/fsi/fsi.h
 create mode 100644 drivers/fsi/fsi_private.h
 create mode 100644 drivers/fsi/fsicfam.h
 create mode 100644 drivers/fsi/fsimaster.c
 create mode 100644 drivers/fsi/fsimaster.h

drivers/fsi/Makefile +1 -1

index f547c08..9800c15 100644
@@ -2,4 +2,4 @@
 # Makefile for the FSI bus specific drivers.
 #
 
-obj-y          += fsiinit.o
+obj-y          += fsiinit.o fsimaster.o

drivers/fsi/fsi.h new file +32 -0

new file mode 100644
index 0000000..f146396
@@ -0,0 +1,32 @@
+/*
+ * FSI device driver structure definitions and defines
+ *
+ * Copyright 2016 IBM Corp.
+ *
+ * Christopher Bostic <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+#ifndef DRIVERS_FSI_H
+#define DRIVERS_FSI_H
+
+#include <linux/device.h>
+
+struct fsimap {
+       u8 link;                        /* Master link # */
+       u8 cfam;                        /* CFAM # on link */
+       u32 offset;                     /* Address offset into CFAM */
+       u32 va;                         /* Virtual address */
+};
+
+struct fsidevice {
+       u32 irq_start;                  /* IRQ Number */
+       struct fsidevice *parent;       /* Parent of this device */
+       struct device dev;              /* LDM entry for bus */
+       struct fsimap map;              /* Address & location info */
+};
+
+#endif /* DRIVERS_FSI_H */

drivers/fsi/fsi_private.h new file +73 -0

new file mode 100644
index 0000000..be327ef
@@ -0,0 +1,97 @@
+/*
+ * FSI device driver structure definitions and defines
+ *
+ * Copyright 2016 IBM Corp.
+ *
+ * Christopher Bostic <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+#ifndef DRIVERS_FSI_PRIVATE_H
+#define DRIVERS_FSI_PRIVATE_H
+
+#include "fsi.h"
+
+#define FSIDD_NAME             "fsi"           /* FSI device driver name */
+
+/*
+ * Universal FSI constants - Applicable for any FSI device
+ */
+#define        FSI_MAX_LINKS           64              /* FSI Master # of links */
+#define        FSI_MAX_CASCADE         4               /* # of CFAMS in cascade */
+#define        FSI_MAX_MASTERS         1               /* # of masters in system */
+#define        FSI_LINK_ENG_MASK       0xE0007FFF      /* Used for minor num calcs */
+#define        FSI_MAX_DEPTH           3               /* Max # of links in path */
+#define        FSI_LINK_SHIFT          23                      /* Bits to shift */
+#define        FSI_LINK_SIZE           (1 << FSI_LINK_SHIFT)   /* 8 MB */
+#define        FSI_CFAM_SHIFT          21                      /* Bits to shift */
+#define        FSI_CFAM_SIZE           (1 << FSI_CFAM_SHIFT)   /* 2 MB */
+#define        FSI_ENGINE_SHIFT        10                      /* Bits to shift */
+#define        FSI_ENGINE_SIZE         (1 << FSI_ENGINE_SHIFT) /* 1 KB */
+#define        FSI_LINK_MASK           0x1f800000              /* Bits for link */
+#define        FSI_CFAM_MASK           0x00600000              /* Bits for cfam */
+#define        FSI_ENGINE_MASK         0x000ffc00              /* Bits for engine */
+#define        FSI_PEEK_OFFSET         FSI_ENGINE_SIZE
+#define        FSI_SLAVE0_OFFSET       (2 * FSI_ENGINE_SIZE)
+#define        FSI_SLV_NO_ERROR        100             /* Slave has no error data */
+#define        FSI_BREAK               0xc0de0000      /* BREAK command */
+#define        FSI_TERM                0xecc00000      /* TERM command */
+#define        FSI_BREAK_TIME          180             /* # Seconds to allow BREAKs */
+#define        FSI_BREAK_CNT           3               /* limit for BREAK attempts */
+#define        FSI_PRIM                0               /* Generic Primary FSI master */
+#define        FSI_MBIT_MASK           0x3             /* FSI master  bits in pa */
+#define        FSI_ENG_MASK            0x00007FFF      /* The engine mask in MATRB */
+/* FSI Events */
+#define FSI_EVT_PLUG           6               /* Device plugged */
+#define FSI_LINK_BUILD         10              /* In build up phase */
+#define FSI_LINK_PROBE         11              /* In probing phase */
+
+/*
+ * Return the link number where this device is attached
+ */
+static inline int fsi_my_link(struct fsidevice *fdev)
+{
+       return fdev->map.link;
+}
+
+/*
+ * Return CFAM number on link where this device is attached
+ */
+static inline int fsi_my_cfam(struct fsidevice *fdev)
+{
+       return fdev->map.cfam;
+}
+
+/*
+ * Determine the link address to send the break command to
+ * This is master dependent
+ */
+static inline int fsi_mtype_2break_id(u8 mtype)
+{

drivers/fsi/fsi_private.h new file +14 -0

+}
+
+/*
+ * Various function prototypes
+ */
+int slv_install(void);
+void slv_uninstall(void);
+
+void fsi_exit_fileio(dev_t);
+
+int fsibus_init(void);
+void fsibus_exit(void);
+
+#endif /* DRIVERS_FSI_PRIVATE_H */

drivers/fsi/fsicfam.h new file +28 -0

new file mode 100644
index 0000000..dde7036
@@ -0,0 +1,46 @@
+/*
+ * FSI CFAM structure definitions and defines
+ *
+ * Copyright 2016 IBM Corp.
+ *
+ * Christopher Bostic <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+#ifndef DRIVERS_FSICFAM_H
+#define DRIVERS_FSICFAM_H
+
+#include "fsi.h"
+#include "fsi_private.h"
+
+#define FSI_MAX_ENGINES                32      /* Max # of engines per CFAM */
+
+struct fsicfam {                       /* CFAM internal structure */
+       struct fsidevice *engines[FSI_MAX_ENGINES];     /* CFAM engine data */
+       u32 cfgtab[FSI_MAX_ENGINES];    /* Configuration word */
+       u16 chipid;                     /* CFAM chip type (IOU, CFAM-S, etc) */
+       u8 id;                          /* CFAM Id */
+       bool has_submaster;             /* CFAM with cascaded or hub masters */
+       bool has_mux;                   /* CFAM with multiplexer */
+       u8 ec_maj;                      /* Major EC Level */

drivers/fsi/fsicfam.h new file +8 -0

+
+/*
+ * CFAM specific function prototypes.
+ */
+int fsi_cfamirq_request(int, struct fsicfam *);
+void fsi_cfamirq_free(struct fsicfam *);
+
+#endif /* DRIVERS_FSICFAM_H */

drivers/fsi/fsiinit.c +4 -0

index 767c0c3..c589294 100644
@@ -13,7 +13,9 @@
 
 #include <linux/init.h>
 #include <linux/module.h>
+#include <linux/kdev_t.h>
 #include "fsiinit.h"
+#include "fsimaster.h"
 
 MODULE_AUTHOR("Christopher Bostic [email protected]");
 MODULE_DESCRIPTION("FSI master device driver");

@@ -26,6 +28,7 @@ MODULE_DESCRIPTION("FSI master device driver");
 struct fsidd fsidd = {         /* FSI device driver structure definition */
        .magic = FSI_DD_MAGIC,
        .strno = FSI_DD_STRNO,
+       .major = MKDEV(FSIDD_MAJOR, 0),
 };
 
 static int fsi_start(void)

@@ -33,6 +36,25 @@ static int fsi_start(void)
        int rc = 0;
 
        dev_dbg(&fsidd.dev, "FSI DD v:%d installation ok\n", FSIDD_VERNO);
+

drivers/fsi/fsiinit.c +0 -0

 }
 

drivers/fsi/fsiinit.h +2 -0

index 93662533..10ddfc0 100644
@@ -19,6 +19,7 @@
 #include <linux/device.h>
 #include <linux/workqueue.h>
 #include <linux/hrtimer.h>
+#include "fsimaster.h"
 
 #define FSI_DD_MAGIC   0x64644632      /* ddF2 */
 #define FSI_DD_STRNO   0x1             /* Structure version number */

@@ -34,6 +35,7 @@ struct fsidd {                                /* FSI Main structure */
        wait_queue_head_t link_wq;      /* Wait queue for link changes */
        unsigned long state;            /* State driver is in */
        struct device dev;              /* Anchor point in /sys/kernel */
+       struct fsimaster pri_master;    /* Primary FSI master */
 };
 
 #define        to_fsidd_prim(a)        container_of(a, struct fsidd, pri_master)

drivers/fsi/fsimaster.c new file +34 -0

new file mode 100644
index 0000000..b5d16db
@@ -0,0 +1,242 @@
+/*
+ * FSI Master Control
+ *
+ * Copyright 2016 IBM Corp.
+ *
+ * Christopher Bostic <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#include <linux/err.h>
+#include <linux/delay.h>
+#include <linux/ktime.h>
+#include <linux/io.h>
+#include "fsi.h"
+#include "fsiinit.h"
+#include "fsimaster.h"
+#include "fsicfam.h"
+
+static int hpinfo_alloc(struct fsimaster *master)
+{
+       return 0;
+}
+
+static inline unsigned int fsimid(struct fsimaster *master)
+{
+       return master->myid;
+}
+
+static void primaster_exit(struct fsimaster *master)
+{

drivers/fsi/fsimaster.c new file +198 -0

+ */
+static u32 virt_master_readreg(struct fsi_mreg *mbase, int regnm)
+{
+       u32 *base = (u32 *)mbase;
+
+       return *(base + regnm);
+}
+
+static void virt_master_readreg2(struct fsi_mreg *mbase, int regnm, u64 *dest)
+{
+       u32 *base = (u32 *)mbase;
+
+       memcpy(dest, base + regnm, sizeof(u64));
+}
+
+static void virt_master_readreg4(struct fsi_mreg *mbase, int regnm, u32 *dest)
+{
+       u32 *base = (u32 *)mbase;
+
+       memcpy(dest, base + regnm, 4 * sizeof(u32));
+}
+
+static void writereg_array(struct fsi_mreg *mbase, int regnm,
+                          u32 *val, size_t size)
+{
+       int i;
+       u32 r_value, new_value[size];
+       u32 *base = (u32 *)mbase;
+
+       if (regnm == FSI_N_MRESB0) {
+               /* A write to the reset register clears out MESRB */
+               *(base + regnm) = 0;
+               return;
+       }
+
+       for (i = 0, base += regnm; i < size; ++i) {
+               new_value[i] = *(val + i);
+
+               /*
+                * The master control registers have various modes when
+                * written; direct copy or set/clear under mask
+                */
+               if (FSI_CLEAR_UNDER_MASK(regnm)) {
+                       r_value = virt_master_readreg(mbase, regnm);
+                       new_value[i] = r_value &= ~(*(val + i));
+               } else if (FSI_SET_UNDER_MASK(regnm)) {
+                       r_value = virt_master_readreg(mbase, regnm);
+                       new_value[i] = r_value |= *(val + i);
+               }
+               /*
+                * If not set or clear under mask type register then simply
+                * copy value
+                */
+               *base++ = new_value[i];
+       }
+}
+
+static void virt_master_writereg(struct fsi_mreg *base, int regnm, u32 val)
+{
+       writereg_array(base, regnm, &val, 1);
+}
+
+static void virt_master_writereg2(struct fsi_mreg *base, int regnm, u64 *val)
+{
+       writereg_array(base, regnm, (u32 *)val, 2);
+}
+
+static void virt_master_writereg8(struct fsi_mreg *base, int regnm, u32 *val)
+{
+       writereg_array(base, regnm, val, 8);
+}
+
+static int primaster_init(struct fsimaster *master)
+{
+       master->read_reg = virt_master_readreg;
+       master->read_reg2 = virt_master_readreg2;
+       master->read_reg4 = virt_master_readreg4;
+       master->write_reg = virt_master_writereg;
+       master->write_reg2 = virt_master_writereg2;
+       master->write_reg8 = virt_master_writereg8;
+       master->maxlinks = PRI_MAX_LINKS;
+       master->have_peek = true;
+       master->irqbase = 0;
+       memset(&master->base, 0, sizeof(struct fsi_mreg));
+       master->dcr_alloc = true;
+       if (hpinfo_alloc(master))
+               primaster_exit(master);
+
+       return master->base ? 0 : 1;
+}
+
+static int fsimaster_init(struct fsimaster *master)
+{
+       int rc = 0;
+
+       memset(&master->quirks, 0, sizeof(struct master_quirks));
+       master->quirks.break_cfam_id = fsi_mtype_2break_id(master->type);
+       master->cfam_size = 0;
+       master->m_get = NULL;
+       master->m_pa2irq = NULL;
+       master->m_exit = NULL;
+
+       rc = primaster_init(master);
+
+       return rc;
+}
+
+struct fsimaster *fsimaster_get_top_master(struct fsimaster *master)
+{
+       struct fsimaster *parent = NULL;
+
+       while (master) {
+               parent = master;
+               master = master->parent;
+       }
+
+       return parent;
+}
+
+static int fsimaster_reset(struct fsimaster *master)
+{
+       u32 reg = 0;
+       u64 reg2 = 0;
+       int rc = 0;
+       struct fsidd *dd = NULL;
+
+       dd = to_fsidd_prim(fsimaster_get_top_master(master));
+
+       reg = master->read_reg(master->base, FSI_N_MVER);
+       if (fsi_mver_extlink(reg) != master->maxlinks) {
+               rc = -EINVAL;
+               goto out;
+       }
+       /* Reset all bridges and ports */
+       reg = FSI_MRESP_RST_ALL_MSTR | FSI_MRESP_RST_ALL_LINK
+               | FSI_MRESP_RST_MCR | FSI_MRESP_RST_PYE;
+       master->write_reg(master->base, FSI_N_MRESP0, reg);
+
+       /* Set up control */
+       reg = (master->type == FSI_PRIM) ? FSI_MECTRL_FPME : FSI_MECTRL_EOAE;
+       master->write_reg(master->base, FSI_N_MECTRL, reg);
+
+       /* Set up mode */
+       reg = fsi_mmode_crs0(1) | fsi_mmode_crs1(1);
+       master->write_reg(master->base, FSI_N_MMODE, reg);
+
+       /* Set up delay characteristics */
+       master->write_reg(master->base, FSI_N_MDLYR, FSI_MDLYR_DFLT);
+
+       /* Enable all links for a short time */
+       reg2 = ~0;
+       master->write_reg2(master->base, FSI_N_MSENP0, &reg2);
+
+       mdelay(1);
+       master->write_reg2(master->base, FSI_N_MCENP0, &reg2);
+
+       reg2 = FSI_MRESP_RST_ALL_MSTR | FSI_MRESP_RST_ALL_LINK;
+       master->write_reg(master->base, FSI_N_MRESP0, reg2);
+out:
+       return rc;
+}
+
+struct fsimaster *fsimaster_build_init(struct fsimaster *master, int type,
+                                      struct fsidevice *parent)
+{
+       int rc = 0;
+       struct fsidd *dd = NULL;
+
+       if (!master)
+               goto out;
+       if (!parent)
+               dd = to_fsidd_prim(master);
+       else {
+               struct fsicfam *cfam = to_fsicfam(parent->parent);
+
+               dd = to_fsidd_prim(fsimaster_get_top_master(cfam->master));
+       }
+       master->type = type;
+       master->fsidev = parent;
+       if (fsimaster_init(master)) {
+               master = NULL;
+               goto out;
+       }
+       if (fsimaster_reset(master)) {
+               rc = -EIO;
+               master = NULL;
+               goto out;
+       }
+out:
+       return master ? : ERR_PTR(rc);
+}
+
+/*
+ * Kick off the master so it can start probing for attached CFAMs
+ */
+void fsimaster_start(struct fsimaster *master)
+{
+}

drivers/fsi/fsimaster.h new file +655 -1

new file mode 100644
index 0000000..4df2caf
@@ -0,0 +1,655 @@
+/*
+ * FSI Master device driver structure definitions and defines
+ *
+ * Copyright 2016 IBM Corp.
+ *
+ * Christopher Bostic <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+#ifndef DRIVERS_FSIMASTER_H
+#define DRIVERS_FSIMASTER_H
+
+#include "fsi_private.h"
+#include "fsi.h"
+#include "fsicfam.h"
+
+#define FSI_MAX_PING_ATTEMPTS  12
+#define        FSI_PLUG_CHECK_TIME     100
+#define FSI_DFLT_IPOLL_CHECK   800
+
+/* FSI master register numbers */
+#define        FSI_N_MMODE     0       /* 0x0   R/W: mode register */
+#define        FSI_N_MDLYR     1       /* 0x4   R/W: delay register */
+#define        FSI_N_MCRSP0    2       /* 0x8   R/W: clock rate selector register 0 */
+#define        FSI_N_MCRSP32   3       /* 0xC   R/W: clock rate selector register 1 */
+#define        FSI_N_MENP      4       /* 0x10  R/W: enable clock register 0 */
+#define        FSI_N_MENP32    5       /* 0x14  R/W: enable clock register 1 */
+#define        FSI_N_MLEVP     6       /* 0x18  R: static level register 0 */
+#define        FSI_N_MLEVP32   7       /* 0x1C  R: static level register 1 */
+#define        FSI_N_MSENP0    6       /* 0x18  S: set enable clock register 0 */
+#define        FSI_N_MREFP0    8       /* 0x20  R: link reference register 0 */
+#define        FSI_N_MCENP0    8       /* 0x20  W: clear enable port register 0 */
+#define        FSI_N_MHPMP0    10      /* 0x28  R: hot plug reference register 0 */
+#define        FSI_N_MCHPMP0   10      /* 0x28  W: clear hot plug reference reg 0 */
+#define        FSI_N_MSIEP0    12      /* 0x30  R/W: Ipoll register 0 */
+#define        FSI_N_MSIEP32   16      /* 0x40  R/W: Ipoll register 4 */
+#define        FSI_N_MAESP0    20      /* 0x50  R: any error port register 0 */
+#define        FSI_N_MAESP32   24      /* 0x60  R: any error port register 4 */
+#define        FSI_N_MSSIEP0   20      /* 0x50  W: set Ipoll register 0 */
+#define        FSI_N_MAEB      28      /* 0x70  R: any error bridge */
+#define        FSI_N_MVER      29      /* 0x74  R: version register */
+#define        FSI_N_MBSYP0    30      /* 0x78  R: port busy register 0 */
+#define        FSI_N_MCSIEP0   28      /* 0x70  W: clear Ipoll register 0 */
+#define        FSI_N_MDRSB1    36      /* 0x90  R/W: DMA select register master 1 */
+#define        FSI_N_MSTAP0    52      /* 0xd0  R: port status reg 0-63 (0xd0-0x1cc) */
+#define        FSI_N_MRESP0    52      /* 0xd0  W: port reset regr 0-63 (0xd0-0x1cc) */
+#define        FSI_N_MESRB0    116     /* 0x1d0 R: error syndrome register 0-16 */
+#define        FSI_N_MRESB0    116     /* 0x1d0 W: reset reg master 0-16 (x1d0-x210) */
+#define        FSI_N_MSCSB0    117     /* 0x1d4 R: master sub cmd stack register 0 */
+#define        FSI_N_MATRB0    118     /* 0x1d8 R: master address trace register 0 */
+#define        FSI_N_MDTRB0    119     /* 0x1dc R: master data trace register 0 */
+#define        FSI_N_MECTRL    184     /* 0x2e0 R/W: error control register master 0 */
+#define        FSI_N_MAESP_SZ  8       /* # of error port register 0-7 */
+
+#define FSI_MSIEP_REG_COUNT    8
+#define PRI_MAX_LINKS          FSI_MAX_LINKS
+
+/*
+ * Model clear under mask (CU) and set under mask (SU) Read only (RO)
+ * and Write only (WO) behavior for virtual Primary FSI Master
+ */
+#define FSI_CLEAR_UNDER_MASK(x)  ((x) == FSI_N_MCENP0 \
+                       || ((x) == FSI_N_MCENP0 + 1)  \
+                       ||  (x) == FSI_N_MCHPMP0      \
+                       || ((x) == FSI_N_MCHPMP0 + 1) \
+                       ||  (x) == FSI_N_MCSIEP0      \
+                       || ((x) == FSI_N_MCSIEP0 + 1) \
+                       || ((x) == FSI_N_MCSIEP0 + 2) \
+                       || ((x) == FSI_N_MCSIEP0 + 3) \
+                       || ((x) == FSI_N_MCSIEP0 + 4) \
+                       || ((x) == FSI_N_MCSIEP0 + 5) \
+                       || ((x) == FSI_N_MCSIEP0 + 6) \
+                       || ((x) == FSI_N_MCSIEP0 + 7))
+#define FSI_SET_UNDER_MASK(x)  ((x) == FSI_N_MSENP0   \
+                       || ((x) == FSI_N_MSENP0 + 1)  \
+                       ||  (x) == FSI_N_MSSIEP0      \
+                       || ((x) == FSI_N_MSSIEP0 + 1) \
+                       || ((x) == FSI_N_MSSIEP0 + 2) \
+                       || ((x) == FSI_N_MSSIEP0 + 3) \
+                       || ((x) == FSI_N_MSSIEP0 + 4) \
+                       || ((x) == FSI_N_MSSIEP0 + 5) \
+                       || ((x) == FSI_N_MSSIEP0 + 6) \
+                       || ((x) == FSI_N_MSSIEP0 + 7))
+
+/*
+ * Return FSI master error information register number for master x
+ */
+static inline int fsi_mesrb_nr(int master)
+{
+       return (FSI_N_MESRB0 + master * 4);
+}
+
+/*
+ * Return FSI master reset register number for master x
+ */
+static inline int fsi_mresb_nr(int master)
+{
+       return FSI_N_MRESB0 + master;
+}
+
+/*
+ * Return FSI master port status register number for link x
+ */
+static inline int fsi_mstap_nr(int link)
+{
+       return FSI_N_MSTAP0 + link;
+}
+
+/*
+ * Return FSI master port error reset register number for link x
+ */
+static inline int fsi_mresp_nr(int link)
+{
+       return FSI_N_MRESP0 + link;
+}
+
+/*
+ * Return FSI master ipoll register number for index x
+ */
+static inline int fsi_msiep_nr(int idx)
+{
+       return FSI_N_MSIEP0 + idx;
+}
+
+/*
+ * Return FSI master error information register number for master x
+ */
+static inline int fsi_maesp_nr(int portreg)
+{
+       return FSI_N_MAESP0 + portreg;
+}
+
+struct fsi_mei {               /* FSI master error information */
+       u32 mesrb;              /* Master error status register */
+       u32 mscsb;              /* Subcommand stack register */
+       u32 matrb;              /* Address trace register */
+       u32 mdtrb;              /* Data trace register */
+};
+
+/* FSI Master register set */
+struct fsi_mreg {
+       u32 mmode;                      /* 0x0 */
+       u32 mdlyr;                      /* 0x4 */
+       u64 mcrsp;                      /* 0x8 - 0xc */
+       u64 menp;                       /* 0x10 - 0x14 */
+       u64 mlevp;                      /* 0x18 - 0x1c */
+       u64 mrefp;                      /* 0x20 - 0x24 */
+       u64 mhpmp;                      /* 0x28 - 0x2c */
+       u32 msiep0[8];                  /* 0x30 - 0x4c */
+       u32 maesp0[8];                  /* 0x50 - 0x6c */
+       u32 maeb0[8];                   /* 0x70 - 0x8c */
+       u32 mdrsb0[16];                 /* 0x90 - 0xcc */
+       u32 mstap0[FSI_MAX_LINKS];      /* 0xd0 - 0x1cc */
+       struct fsi_mei mresb0[FSI_MAX_MASTERS]; /* 0x1d0 - 0x2dc */
+       u32 mectrl;                     /* 0x2e0 */
+       u32 mver;                       /* Master version ID, read only */
+};
+
+#define PORT_BUSY_CHECKS_MAX   10
+
+/* FSI Port controller reset types */
+#define        FSI_PORT_GENERAL_RESET          0x80000000
+#define        FSI_PORT_ERROR_RESET            0x40000000
+#define        FSI_PORT_GENERAL_RESET_BRIDGE   0x20000000
+#define        FSI_PORT_GENERAL_RESET_PORT     0x10000000
+#define        FSI_PORT_RESET_CNTRL_REGS       0x08000000
+#define        FSI_PORT_RESET_PA_ERROR         0x04000000
+
+/* FSI Port controller error masks */
+#define        FSI_PORT_EMASK_ID0      0xf0000000
+#define        FSI_PORT_EMASK_ID1      0x0f000000
+#define        FSI_PORT_EMASK_ID2      0x00f00000
+#define        FSI_PORT_EMASK_ID3      0x000f0000
+#define        FSI_PORT_CRCMASK        0x0000f000
+#define        FSI_PORT_HOTPLUG        0x00000800
+
+/*
+ * FSI Slave interrupt enable/disable bit setting. Return the bit setting
+ * given a link and cfam number. The result of this function can be input
+ * to the mssiepX and mcsiepX registers or or'ed in to msiepX.
+ * The formula is 1 << 31 - (link % 8 * 4 + cfam).
+ *
+ * Not in FSI Spec (0..30):
+ * MSIEPx register bit 0 is port 0 and cfam 0.
+ * MSIEPx register bit 1 is port 0 and cfam 1.
+ * MSIEPx register bit 31 is port 7 and cfam 3.
+ */
+static inline u32 fsi_mk_msiep(int link, int cfam)
+{
+       return mask32((link % (BITS_PER_LONG / FSI_MAX_CASCADE))
+                     * FSI_MAX_CASCADE + cfam);
+}
+
+/*
+ * Return mask for all CFAMs id x to 3 (end of cascade) on a specific link.
+ */
+static inline u32 fsi_mk_msiep_plus(int link, int cfam)
+{
+       u32 bits = (0xf >> cfam) << 28;
+
+       return bits >> (link % (BITS_PER_LONG / FSI_MAX_CASCADE)
+                       * FSI_MAX_CASCADE);
+}
+
+/*
+ * Return mask for all CFAMs on a specific link.
+ */
+static inline u32 fsi_mk_msiep_all(int link)
+{
+       return 0xf0000000 >> (link % (BITS_PER_LONG / FSI_MAX_CASCADE)
+                             * FSI_MAX_CASCADE);
+}
+
+/*
+ * Return index for msiepX register
+ */
+static inline int fsi_mk_msiep_idx(int link)
+{
+       return link / (BITS_PER_LONG / FSI_MAX_CASCADE);
+}
+
+/*
+ * FSI Master Mode register setting
+ */
+#define        FSI_MMODE_EIP           0x80000000      /* Enable interrupt polling */
+#define        FSI_MMODE_ECRC          0x40000000      /* Enable hw error recovery */
+#define        FSI_MMODE_ERAC          0x20000000      /* Enable relative addr cmds */
+#define        FSI_MMODE_EPC           0x10000000      /* Enable parity checking */
+#define        FSI_MMODE_CRS0SHFT      18              /* Clock select 0 mask shift */
+#define        FSI_MMODE_CRS0MASK      0x3ff           /* Clock select 0 mask */
+#define        FSI_MMODE_CRS1SHFT      8               /* Clock select 1 mask shift */
+#define        FSI_MMODE_CRS1MASK      0x3ff           /* Clock select 1 mask */
+#define        FSI_MMODE_P63           0x80            /* Route link 63 IOU slave C */
+#define        FSI_MMODE_DIV4          0x00000040      /* Divide by 4 (legacy mode) */
+
+/*
+ * Rolf Fritz Nov 20, 2013:
+ *     MSB=1, LSB=0 is 0.8 ms
+ *     MSB=0, LSB=1 is 0.9 ms
+ */
+#define        FSI_MMODE_P8_TO_MSB     0x00000020      /* Timeout val most sig bit */
+#define        FSI_MMODE_P8_TO_LSB     0x00000010      /* Timeout val least sig bit */
+
+static inline u32 fsi_mmode_crs0(u32 x)
+{
+       return (x & FSI_MMODE_CRS0MASK) << FSI_MMODE_CRS0SHFT;
+}
+
+static inline u32 fsi_mmode_crs1(u32 x)
+{
+       return (x & FSI_MMODE_CRS1MASK) << FSI_MMODE_CRS1SHFT;
+}
+
+static inline u32 fsi_mmode_extcrs0(u32 x)
+{
+       return (x >> FSI_MMODE_CRS0SHFT) & FSI_MMODE_CRS0MASK;
+}
+
+static inline u32 fsi_mmode_extcrs1(u32 x)
+{
+       return (x >> FSI_MMODE_CRS1SHFT) & FSI_MMODE_CRS1MASK;
+}
+
+/*
+ * FSI master delay register
+ */
+#define        FSI_MDLYR_ECHO0_SHFT    28      /* Selection 0 echo delay cycles */
+#define        FSI_MDLYR_ECHO0_MASK    0xf     /* Selection 0 echo delay cycles */
+#define        FSI_MDLYR_SEND0_SHFT    24      /* Selection 0 send delay cycles */
+#define        FSI_MDLYR_SEND0_MASK    0xf     /* Selection 0 send delay cycles */
+#define        FSI_MDLYR_ECHO1_SHFT    20      /* Selection 1 echo delay cycles */
+#define        FSI_MDLYR_ECHO1_MASK    0xf     /* Selection 1 echo delay cycles */
+#define        FSI_MDLYR_SEND1_SHFT    16      /* Selection 1 send delay cycles */
+#define        FSI_MDLYR_SEND1_MASK    0xf     /* Selection 1 send delay cycles */
+#define        FSI_MDLYR_DFLT          0xffff0000 /* Default setting */
+
+static inline int fsi_mdlyr_echo0(int x)
+{
+       return (x & FSI_MDLYR_ECHO0_MASK) << FSI_MDLYR_ECHO0_SHFT;
+}
+
+static inline int fsi_mdlyr_echo1(int x)
+{
+       return (x & FSI_MDLYR_ECHO1_MASK) << FSI_MDLYR_ECHO1_SHFT;
+}
+
+static inline int fsi_mdlyr_send0(int x)
+{
+       return (x & FSI_MDLYR_SEND0_MASK) << FSI_MDLYR_SEND0_SHFT;
+}
+
+static inline int fsi_mdlyr_send1(int x)
+{
+       return (x & FSI_MDLYR_SEND1_MASK) << FSI_MDLYR_SEND1_SHFT;
+}
+
+static inline int fsi_mdlyr_extecho0(u32 x)
+{
+       return (x >> FSI_MDLYR_ECHO0_SHFT) & FSI_MDLYR_ECHO0_MASK;
+}
+
+static inline int fsi_mdlyr_extecho1(u32 x)
+{
+       return (x >> FSI_MDLYR_ECHO1_SHFT) & FSI_MDLYR_ECHO1_MASK;
+}
+
+static inline int fsi_mdlyr_extsend0(u32 x)
+{
+       return (x >> FSI_MDLYR_SEND0_SHFT) & FSI_MDLYR_SEND0_MASK;
+}
+
+static inline int fsi_mdlyr_extsend1(u32 x)
+{
+       return (x >> FSI_MDLYR_SEND1_SHFT) & FSI_MDLYR_SEND1_MASK;
+}
+
+/*
+ * MAEB Register
+ */
+#define        FSI_MASTER0             0x80000000      /* Primary Master */
+
+/*
+ * MVER Register
+ */
+#define        FSI_MVER_VER_MASK       0xff    /* FSI master version mask */
+#define        FSI_MVER_VER_SHFT       24      /* FSI master version shift */
+#define        FSI_MVER_BRG_MASK       0xff    /* FSI master FSI bridges mask */
+#define        FSI_MVER_BRG_SHFT       16      /* FSI master FSI bridges shift */
+#define        FSI_MVER_LINK_MASK      0xff    /* FSI master links mask */
+#define        FSI_MVER_LINK_SHFT      8       /* FSI master links shift */
+
+static inline int fsi_mver_extversion(u32 x)
+{
+       return (x >> FSI_MVER_VER_SHFT) & FSI_MVER_VER_MASK;
+}
+
+static inline int fsi_mver_extport(u32 x)
+{
+       return (x >> FSI_MVER_BRG_SHFT) & FSI_MVER_BRG_MASK;
+}
+
+static inline int fsi_mver_extlink(u32 x)
+{
+       return (x >> FSI_MVER_LINK_SHFT) & FSI_MVER_LINK_MASK;
+}
+
+/*
+ * Master reset types
+ */
+#define        FSI_MRESB_RST_GEN       0x80000000      /* General reset */
+#define        FSI_MRESB_RST_ERR       0x40000000      /* Error Reset, don't use */
+#define        FSI_MRESB_DELAY         0x01000000      /* do delay settings */
+
+/*
+ * Port reset types
+ */
+#define        FSI_MRESP_RST_GEN       0x80000000      /* General reset */
+#define        FSI_MRESP_RST_ERR       0x40000000      /* Error Reset, don't use */
+#define        FSI_MRESP_RST_ALL_MSTR  0x20000000      /* Reset all FSI masters */
+#define        FSI_MRESP_RST_ALL_LINK  0x10000000      /* Reset all FSI port contr. */
+#define        FSI_MRESP_RST_MCR       0x08000000      /* Reset FSI master reg. */
+#define        FSI_MRESP_RST_PYE       0x04000000      /* Reset FSI parity error */
+#define        FSI_MRESP_RST_ALL       0xfc000000      /* Reset any error */
+
+/*
+ * MESRB Register
+ */
+#define        FSI_MESRB_EC_MASK       0xf             /* Error code mask */
+#define        FSI_MESRB_EC_SHFT       28              /* Error code shift */
+#define        FSI_MESRB_PARITY_MASK   0xff            /* Parity bits shift */
+#define        FSI_MESRB_PARITY_SHFT   16              /* Parity bits Mask */
+#define        FSI_MESRB_CRC_MASK      0xf             /* CRC mask */
+#define        FSI_MESRB_CRC_SHFT      24              /* CRC shift */
+#define        FSI_MESRB_RESERVED_MASK 0xffff          /* Reserved mask */
+#define        FSI_MESRB_OPB_PYE       0x0001000       /* OPB Parity Error */
+#define        FSI_MESRB_NE            0               /* No error */
+#define        FSI_MESRB_OPBE          1               /* OPB Error */
+#define        FSI_MESRB_IOPBS         2               /* Illegal OPB state */
+#define        FSI_MESRB_PAE           3               /* Port access error */
+#define        FSI_MESRB_IDM           4               /* ID mismatch */
+#define        FSI_MESRB_DMASE         5               /* DMA select error */
+#define        FSI_MESRB_PTOE          6               /* Port time out error */
+#define        FSI_MESRB_MTOE          7               /* Master time out error */
+#define        FSI_MESRB_MCRCE         8               /* Master CRC error */
+#define        FSI_MESRB_ERRA          9               /* Any error response */
+#define        FSI_MESRB_ERRC          10              /* CRC error response */
+#define        FSI_MESRB_PE            11              /* Protocol error */
+#define        FSI_MESRB_PYE           12              /* Parity err/Reg access err */
+#define        FSI_MESRB_LAST          (FSI_MESRB_PYE + 1)     /* Last entry */
+
+/* Extract error conditon */
+static inline u32 fsi_mesrb_extec(u32 x)
+{
+       return (x >> FSI_MESRB_EC_SHFT) & FSI_MESRB_EC_MASK;
+}
+
+/* Extract CRC error counter */
+static inline u32 fsi_mesrb_extcrc(u32 x)
+{
+       return (x >> FSI_MESRB_CRC_SHFT) & FSI_MESRB_CRC_MASK;
+}
+
+/* Extract parity error bits */
+static inline u32 fsi_mesrb_extparity(u32 x)
+{
+       return (x >> FSI_MESRB_PARITY_SHFT) & FSI_MESRB_PARITY_MASK;
+}
+
+/*
+ * MATRB Register
+ */
+#define        FSI_MATRB_LPA_MASK              0x3f    /* Last port/link addr mask */
+#define        FSI_MATRB_LPA_SHFT              26      /* Last port/link addr shift */
+#define        FSI_MATRB_LSID_MASK             3       /* Last slave id mask */
+#define        FSI_MATRB_LSID_SHFT             24      /* Last slave id shift */
+#define        FSI_MATRB_P8_ADDR_HI_MASK       3       /* Upper 2 bits of addr */
+#define        FSI_MATRB_P8_ADDR_HI_SHFT       24      /* Upper 2 bits of addr shift */
+#define        FSI_MATRB_SLPA_MASK             3       /* Last sublink address mask */
+#define        FSI_MATRB_SLPA_SHFT             19      /* Last sublink address shift */
+#define        FSI_MATRB_SLSID_SHFT            17      /* Last subslave id shift */
+#define        FSI_MATRB_READ_MASK             0x00400000      /* Last cmd was Read */
+#define        FSI_MATRB_ADDR_MASK             0x1fffff        /* Last address mask */
+#define        FSI_MATRB_ADDR_SHFT             1       /* Last address shift */
+#define        FSI_MATRB_P8_ADDR_SHFT          3       /* Non contiguous upper bits */
+#define        FSI_MATRB_DATAS_MASK            1       /* Last addr data size mask */
+#define        FSI_MATRB_CM_MASK               0x00200000      /* Cascaded FSI mask */
+
+/* Extract link number */
+static inline int fsi_matrb_lpa(u32 x)
+{
+       return (x >> FSI_MATRB_LPA_SHFT) & FSI_MATRB_LPA_MASK;
+}
+
+/* Extract data size of last command */
+static inline int fsi_matrb_datasize(u32 x)
+{
+       return x & FSI_MATRB_DATAS_MASK;
+}
+
+/* Extract read/write command */
+static inline int fsi_matrb_isread(u32 x)
+{
+       return x & FSI_MATRB_READ_MASK;
+}
+
+/*
+ * MSTAP Register
+ */
+#define        FSI_MSTAP_MASK          0xf             /* Error mask ID 0..3 */
+#define        FSI_MSTAP_ID0_SHFT      28              /* CFAM 0 error shift */
+#define        FSI_MSTAP_ID1_SHFT      24              /* CFAM 1 error shift */
+#define        FSI_MSTAP_ID2_SHFT      20              /* CFAM 2 error shift */
+#define        FSI_MSTAP_ID3_SHFT      16              /* CFAM 3 error shift */
+#define        FSI_MSTAP_CRC_MASK      0xf             /* CRC mask */
+#define        FSI_MSTAP_CRC_SHFT      12              /* CRC error counter */
+#define        FSI_MSTAP_HOTPLUG       0x800           /* Hotplug indicator */
+#define        FSI_MSTAP_NE            0               /* No error */
+#define        FSI_MSTAP_ERRA          1               /* Any error response */
+#define        FSI_MSTAP_ERRC          2               /* CRC error response */
+#define        FSI_MSTAP_UCRCE         3               /* Port detected CRC error */
+#define        FSI_MSTAP_IDM           4               /* ID mismatch */
+#define        FSI_MSTAP_PTOE          5               /* Port time out error */
+#define        FSI_MSTAP_IIPSE         6               /* Invalid I-Poll state error */
+#define        FSI_MSTAP_LAST          (FSI_MSTAP_IIPSE + 1)   /* Last entry */
+
+/* Extract error reason for slave id 0..3 */
+static inline u32 fsi_mstap_extec(u32 x, int id)
+{
+       return (x >> (FSI_MSTAP_ID0_SHFT - id * FSI_MAX_CASCADE))
+              & FSI_MSTAP_MASK;
+}
+
+/* Extract crc counter */
+static inline u32 fsi_mstap_extcrc(u32 x)
+{
+       return (x >> FSI_MSTAP_CRC_SHFT) & FSI_MSTAP_CRC_MASK;
+}
+
+/*
+ * MECTRL Register
+ */
+#define        FSI_MECTRL_TP_SHFT              24      /* parity error generation */
+#define        FSI_MECTRL_TP_MASK              0xff    /* Mask for parity errors */
+#define        FSI_MECTRL_IPE_SHFT             16      /* Shift inhibit parity error */
+#define        FSI_MECTRL_IPE_MASK             0xff    /* Mask inhibit parity err */
+#define        FSI_MECTRL_EOAE                 0x8000  /* Enable machine check */
+#define        FSI_MECTRL_P8_AUTO_TERM         0x4000  /* Auto terminate */
+#define        FSI_MECTRL_FPME                 0x2000  /* Freeze port on master err */
+#define        FSI_MECTRL_P8_SID_TO_3          0x0800  /* Force slave ID to 3 */
+
+/* Force parity error events */
+static inline u32 fsi_mectrl_fpe(int id)
+{
+       return (id & FSI_MECTRL_TP_MASK) << FSI_MECTRL_TP_SHFT;
+}
+
+/* Inhibit parity errors */
+static inline u32 fsi_mectrl_ipe(int id)
+{
+       return (id & FSI_MECTRL_IPE_MASK) << FSI_MECTRL_IPE_SHFT;
+}
+
+/*
+ * Returns the virtual address of the FSI slave configuration word 0 given
+ * the FSI slave engine 0 virtual address.
+ *
+ * NOTE: Assumes address space is mapped without holes. This is ok as both
+ * engines 2 2KB apart and Linux uses 4KB pages.
+ */
+static inline void *get_termva(void *slv_va)
+{
+       return (void *)((unsigned long)slv_va & ~0xfff);
+}
+
+static inline unsigned long get_termpa(unsigned long slv_pa)
+{
+       return slv_pa & ~0xfff;
+}
+
+struct master_quirks {
+       int break_cfam_id;
+       void (*port_reset)(struct fsidevice *, struct fsidevice *, int);
+       int (*send_break)(struct fsimaster *, void *, int, struct fsicfam *);
+       int (*break_set_cfam_id)(void *, int);
+};
+
+struct fsimaster {                     /* FSI master definition */
+       struct fsimaster *parent;       /* Parent of this master */
+       char name[8];                   /* Name for /sysfs */
+       unsigned long peek40c;          /* Peek engine identifications */
+       u32 membase;                    /* Base MMIO address */
+       int irqbase;                    /* Base IRQ number */
+       struct fsidevice *fsidev;       /* Pointer to fsi cascaded engine */
+       struct fsidevice *fsislv;       /* Pointer to fsi slave engine */
+       struct fsi_mreg *base;          /* Ptr to register space */
+       spinlock_t lock;                /* Lock */
+       bool dcr_alloc;                 /* True if ioremap for dcr reg space */
+       bool have_peek;                 /* True if peek engine read needed */
+       unsigned char myid;             /* FSI master identifier for traces */
+       unsigned char type;             /* Type FSI master */
+       unsigned char hw_version;       /* FSI master hardware version */
+       unsigned char maxlinks;         /* FSI master links */
+       struct fsilink *link[FSI_MAX_LINKS];
+       void (*write_reg)(struct fsi_mreg *, int, u32); /* Write 32 bit word */
+       u32 (*read_reg)(struct fsi_mreg *, int);        /* Read 32 bit word */
+       void (*write_reg2)(struct fsi_mreg *, int, u64 *);      /* 64 bit */
+       void (*read_reg2)(struct fsi_mreg *, int, u64 *);       /* 64 bit */
+       void (*read_reg4)(struct fsi_mreg *, int, u32 *);       /* 4 words */
+       void (*write_reg8)(struct fsi_mreg *, int, u32 *);      /* 8 words */
+       struct fsidevice * (*m_get)(struct fsimaster *, int, int);
+       int (*m_pa2irq)(struct fsimaster *, u32);
+       void (*m_exit)(struct fsimaster *);
+       struct master_quirks quirks;    /* hardware quirks functions/data */
+       unsigned char srsic;            /* master specific register offset */
+       unsigned char srsim;            /* master specific register offset */
+       unsigned long cfam_size;        /* master specific cfam size */
+};
+#define to_fsimaster_probe(a)  \
+                       container_of(a, struct fsimaster, hotp.probework)
+#define to_fsimaster_build(a)  \
+                       container_of(a, struct fsimaster, hotp.buildwork)
+
+/*
+ * Functions to create/delete an FSI Master
+ */
+struct fsimaster *fsimaster_build_init(struct fsimaster *, int,
+                                      struct fsidevice *);
+struct fsimaster *fsimaster_build(int, struct fsidevice *);
+void fsimaster_free(struct fsimaster *);
+void fsimaster_put(struct fsimaster *);
+struct fsimaster *fsimaster_get(struct fsimaster *);
+struct fsimaster *fsimaster_find(u32);
+int fsimaster_plugcheck(u32);
+void fsimaster_start(struct fsimaster *);
+int fsimaster_stop(struct fsimaster *);
+void fsimaster_stopsync(struct fsimaster *);
+int fsi_linkbuild(struct fsimaster *, int);
+int fsi_linkdown(struct fsimaster *, int);
+void fsi_linklost(struct fsimaster *, int);
+
+/*
+ * Master commands
+ */
+int fsi_sendbreak(struct fsimaster *, u32, int);
+struct fsimaster *fsimaster_get_top_master(struct fsimaster *);
+
+/*
+ * FSI master register access functions (without locking)
+ */
+int fsimaster_reseterror_nl(struct fsimaster *, int);
+int fsimaster_resetgeneral_nl(struct fsimaster *, int);
+
+/*
+ * Helper utilities for register access
+ */
+void fsimaster_setspeed(struct fsimaster *, int, int);
+int fsimaster_ipoll_off_link_mask(struct fsimaster *, int, u32 *);
+int fsimaster_ipoll_off_link(struct fsimaster *, int);
+int fsimaster_ipoll_on_link(struct fsimaster *, int, u32);
+void fsimaster_disable_link(struct fsimaster *, int);
+void fsimaster_enable_link(struct fsimaster *, int);
+u64 fsimaster_read_menp(struct fsimaster *);
+u64 fsimaster_read_menp_nl(struct fsimaster *);
+u32 fsimaster_read_mmode(struct fsimaster *);
+u32 fsimaster_read_mmode_nl(struct fsimaster *);
+void fsimaster_read_mcrsp(struct fsimaster *, u64 *);
+int fsimaster_read_msiep(struct fsimaster *);
+int fsimaster_read_msiep_nl(struct fsimaster *);
+int fsimaster_write_msiep(struct fsimaster *, u32 *);
+int fsimaster_write_msiep_nl(struct fsimaster *, u32 *);
+int setup_me(struct fsimaster *, int);
+
+/*
+ * Utilities to decode master error registers
+ */
+int fsi_matrb_lsid(u32);
+unsigned long fsi_matrb_addr(unsigned long);
+
+/*
+ * Helper utilities for link/cfam calculations.
+ */
+u32 fsimaster_cfam2pa(struct fsimaster *, int, int);
+u32 fsimaster_linksz(struct fsimaster *);
+u32 fsimaster_cfamsz(struct fsimaster *);
+
+/*
+ * Helper utilities for IRQ number calculations.
+ */
+int fsimaster_pa2irq(struct fsimaster *, u32);
+int fsi_pa2irq(u32);
+
+/*
+ * Functions for link reference
+ */
+void fsimaster_linkref_add(struct fsimaster *, struct fsilink *);
+struct fsilink *fsimaster_linkref_del(struct fsimaster *, int);
+struct fsilink *fsimaster_linkref_markdel(struct fsimaster *, int);
+struct fsilink *fsimaster_linkget(struct fsimaster *, int);
+struct fsilink *fsimaster_linkget_inirq(struct fsimaster *, int);
+struct fsicfam *fsimaster_cfamget(struct fsimaster *, int, int);
+struct fsidevice *fsimaster_slvget(struct fsimaster *, int, int);
+struct fsidevice *fsimaster_slvget_inirq(struct fsimaster *, int, int);
+struct fsidevice *fsimaster_engget(struct fsimaster *, int, int, int);
+struct fsidevice *fsimaster_engget_inirq(struct fsimaster *, int, int, int);
+void fsimaster_linkput(struct fsilink *);
+void fsimaster_cfamput(struct fsicfam *);
+void fsimaster_slvput(struct fsidevice *);
+void fsimaster_engput(struct fsidevice *);
+void fsi_rst_error2(struct fsimaster *, struct fsidevice *, int, int, int, int);
+int port_reset(struct fsimaster *, int);
+
+#endif /* DRIVERS_FSIMASTER_H */
--

1.8.2.2

Quoted 7 lines · On Thu, Aug 25, 2016 at 5:24 AM, <[email protected]> wrote:

From: Chris Bostic <[email protected]>

Define the FSI master control register set and its accessors. Initialize the primary FSI master.

Signed-off-by Chris Bostic <[email protected]>

---

I recall reading this patch in the past. No changelog?

Quoted 28 lines

 drivers/fsi/Makefile      |   2 +-
 drivers/fsi/fsi.h         |  32 +++
 drivers/fsi/fsi_private.h |  97 +++++++
 drivers/fsi/fsicfam.h     |  46 ++++
 drivers/fsi/fsiinit.c     |  22 ++
 drivers/fsi/fsiinit.h     |   2 +
 drivers/fsi/fsimaster.c   | 242 +++++++++++++++++
 drivers/fsi/fsimaster.h   | 655 ++++++++++++++++++++++++++++++++++++++++++++++
 8 files changed, 1097 insertions(+), 1 deletion(-)
 create mode 100644 drivers/fsi/fsi.h
 create mode 100644 drivers/fsi/fsi_private.h
 create mode 100644 drivers/fsi/fsicfam.h
 create mode 100644 drivers/fsi/fsimaster.c
 create mode 100644 drivers/fsi/fsimaster.h

drivers/fsi/Ma renamed from drivers/fsi/Makefile +5 -0

index f547c08..9800c15 100644
 
 
 
+ * Determine the link address to send the break command to
+ * This is master dependent
+ */
+static inline int fsi_mtype_2break_id(u8 mtype)
+{

drivers/fsi/Ma

Quoted 10 lines

drivers/fsi/Ma renamed from drivers/fsi/Makefile +10 -0

+       return FSI_MAX_CASCADE - 1;
+}
+
+/*
+ * Build a mask where bit index 'x' is set (numbering from left to right.
+ * Bit 0 is MSB and bit 31 is LSM.
+ */
+static inline unsigned long mask32(int x)
+{
+       return 1 << (BITS_PER_LONG - x - 1);

Is this masking in IBM bit ordering?

We should pull the macros (or at least copy them) from arch/powerpc so we can use them here.

Quoted 53 lines

drivers/fsi/Ma renamed from drivers/fsi/Makefile +14 -0

+}
+
+/*
+ * Various function prototypes
+ */
+int slv_install(void);
+void slv_uninstall(void);
+
+void fsi_exit_fileio(dev_t);
+
+int fsibus_init(void);
+void fsibus_exit(void);
+
+#endif /* DRIVERS_FSI_PRIVATE_H */

drivers/fsi/fsicfam.h new file +32 -0

new file mode 100644
index 0000000..dde7036
@@ -0,0 +1,46 @@
+/*
+ * FSI CFAM structure definitions and defines
+ *
+ * Copyright 2016 IBM Corp.
+ *
+ * Christopher Bostic <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+#ifndef DRIVERS_FSICFAM_H
+#define DRIVERS_FSICFAM_H
+
+#include "fsi.h"
+#include "fsi_private.h"
+
+#define FSI_MAX_ENGINES                32      /* Max # of engines per CFAM */
+
+struct fsicfam {                       /* CFAM internal structure */
+       struct fsidevice *engines[FSI_MAX_ENGINES];     /* CFAM engine data */
+       u32 cfgtab[FSI_MAX_ENGINES];    /* Configuration word */
+       u16 chipid;                     /* CFAM chip type (IOU, CFAM-S, etc) */
+       u8 id;                          /* CFAM Id */
+       bool has_submaster;             /* CFAM with cascaded or hub masters */
+       bool has_mux;                   /* CFAM with multiplexer */
+       u8 ec_maj;                      /* Major EC Level */
+       u8 ec_min;                      /* Minor EC Level or version number */
+       u16 pages;                      /* # Mapped pages */
+       u8 no_eng;                      /* Number of engines[] */
+       struct fsidevice fsidev;        /* LDM entry */

drivers/fsi/fsicfam.h line 38

Quoted 6 lines

drivers/fsi/fsicfam.h new file +6 -0

+       struct fsidevice hpdone;        /* Dummy engine to signal completion */
+       unsigned long eng_build;        /* True during engine activate */
+       struct fsimaster *master;       /* pointer to parent master */
+};
+
+#define to_fsicfam(x)  container_of((x), struct fsicfam, fsidev)

Make this a function.

Quoted 36 lines

drivers/fsi/fsicfam.h new file +8 -0

+
+/*
+ * CFAM specific function prototypes.
+ */
+int fsi_cfamirq_request(int, struct fsicfam *);
+void fsi_cfamirq_free(struct fsicfam *);
+
+#endif /* DRIVERS_FSICFAM_H */

drivers/fsi/fsiinit.c +4 -0

index 767c0c3..c589294 100644
@@ -13,7 +13,9 @@
 
 #include <linux/init.h>
 #include <linux/module.h>
+#include <linux/kdev_t.h>
 #include "fsiinit.h"
+#include "fsimaster.h"
 
 MODULE_AUTHOR("Christopher Bostic [email protected]");
 MODULE_DESCRIPTION("FSI master device driver");

@@ -26,6 +28,7 @@ MODULE_DESCRIPTION("FSI master device driver");
 struct fsidd fsidd = {         /* FSI device driver structure definition */
        .magic = FSI_DD_MAGIC,
        .strno = FSI_DD_STRNO,
+       .major = MKDEV(FSIDD_MAJOR, 0),
 };
 
 static int fsi_start(void)

@@ -33,6 +36,25 @@ static int fsi_start(void)
        int rc = 0;
 
        dev_dbg(&fsidd.dev, "FSI DD v:%d installation ok\n", FSIDD_VERNO);
+

drivers/fsi/fsiinit.c static int fsi_start(void) · line 49

Quoted 10 lines

drivers/fsi/fsiinit.c +10 -0

+       init_waitqueue_head(&fsidd.error_wq);
+       init_waitqueue_head(&fsidd.lbus_wq);
+       init_waitqueue_head(&fsidd.irq_wq);
+       init_waitqueue_head(&fsidd.link_wq);
+
+       /*
+        * Initialize the the master
+        */
+       if (!fsimaster_build_init(&fsidd.pri_master, FSI_PRIM, 0)) {
+               rc = PTR_ERR(0);

???

drivers/fsi/fsiinit.c static int fsi_start(void) · line 58

Quoted 9 lines

drivers/fsi/fsiinit.c +8 -0

+               goto err;
+       }
+       fsimaster_start(&fsidd.pri_master);
+       dev_dbg(&fsidd.dev, "FSI DD v%d installation ok\n", FSIDD_VERNO);
+       return rc;
+
+err:
+       dev_dbg(&fsidd.dev, "FSI DD v:%d installation failed\n", FSIDD_VERNO);
        return rc;

Your formatting is broken.

Quoted 67 lines

drivers/fsi/fsiinit.c +0 -0

 }
 

drivers/fsi/fsiinit.h +2 -0

index 93662533..10ddfc0 100644
@@ -19,6 +19,7 @@
 #include <linux/device.h>
 #include <linux/workqueue.h>
 #include <linux/hrtimer.h>
+#include "fsimaster.h"
 
 #define FSI_DD_MAGIC   0x64644632      /* ddF2 */
 #define FSI_DD_STRNO   0x1             /* Structure version number */

@@ -34,6 +35,7 @@ struct fsidd {                                /* FSI Main structure */
        wait_queue_head_t link_wq;      /* Wait queue for link changes */
        unsigned long state;            /* State driver is in */
        struct device dev;              /* Anchor point in /sys/kernel */
+       struct fsimaster pri_master;    /* Primary FSI master */
 };
 
 #define        to_fsidd_prim(a)        container_of(a, struct fsidd, pri_master)

drivers/fsi/fsimaster.c new file +38 -0

new file mode 100644
index 0000000..b5d16db
@@ -0,0 +1,242 @@
+/*
+ * FSI Master Control
+ *
+ * Copyright 2016 IBM Corp.
+ *
+ * Christopher Bostic <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#include <linux/err.h>
+#include <linux/delay.h>
+#include <linux/ktime.h>
+#include <linux/io.h>
+#include "fsi.h"
+#include "fsiinit.h"
+#include "fsimaster.h"
+#include "fsicfam.h"
+
+static int hpinfo_alloc(struct fsimaster *master)
+{
+       return 0;
+}
+
+static inline unsigned int fsimid(struct fsimaster *master)
+{
+       return master->myid;
+}
+
+static void primaster_exit(struct fsimaster *master)
+{
+       if (master->dcr_alloc) {
+               master->base = NULL;
+               master->dcr_alloc = false;
+       }

drivers/fsi/fsimaster.c line 44

Quoted 6 lines

drivers/fsi/fsimaster.c new file +6 -0

+}
+
+/*
+ * Read/write functions to access primary FSI master registers
+ * Note that this master is virtual as we don't yet have any
+ * real FSI masters implemented in hardware

"virtual"? What's the purpose of this code?

Quoted 23 lines

drivers/fsi/fsimaster.c new file +21 -0

+ */
+static u32 virt_master_readreg(struct fsi_mreg *mbase, int regnm)
+{
+       u32 *base = (u32 *)mbase;
+
+       return *(base + regnm);
+}
+
+static void virt_master_readreg2(struct fsi_mreg *mbase, int regnm, u64 *dest)
+{
+       u32 *base = (u32 *)mbase;
+
+       memcpy(dest, base + regnm, sizeof(u64));
+}
+
+static void virt_master_readreg4(struct fsi_mreg *mbase, int regnm, u32 *dest)
+{
+       u32 *base = (u32 *)mbase;
+
+       memcpy(dest, base + regnm, 4 * sizeof(u32));
+}

Quoted 10 lines · Joel Stanley

Quoted 7 lines · On Thu, Aug 25, 2016 at 5:24 AM, <[email protected]> wrote:

From: Chris Bostic <[email protected]>

Define the FSI master control register set and its accessors. Initialize the primary FSI master.

Signed-off-by Chris Bostic <[email protected]>

---

I recall reading this patch in the past. No changelog?

Had the changes specific to this patch in 0001, will move those to 0002.

Quoted 41 lines

Quoted 28 lines

drivers/fsi/Makefile      |   2 +-
drivers/fsi/fsi.h         |  32 +++
drivers/fsi/fsi_private.h |  97 +++++++
drivers/fsi/fsicfam.h     |  46 ++++
drivers/fsi/fsiinit.c     |  22 ++
drivers/fsi/fsiinit.h     |   2 +
drivers/fsi/fsimaster.c   | 242 +++++++++++++++++
drivers/fsi/fsimaster.h   | 655 ++++++++++++++++++++++++++++++++++++++++++++++
8 files changed, 1097 insertions(+), 1 deletion(-)

create mode 100644 drivers/fsi/fsi.h
create mode 100644 drivers/fsi/fsi_private.h
create mode 100644 drivers/fsi/fsicfam.h
create mode 100644 drivers/fsi/fsimaster.c
create mode 100644 drivers/fsi/fsimaster.h

drivers/fsi/Ma renamed from drivers/fsi/Makefile +5 -0

index f547c08..9800c15 100644
 
 
 
+ * Determine the link address to send the break command to
+ * This is master dependent
+ */
+static inline int fsi_mtype_2break_id(u8 mtype)
+{

drivers/fsi/Ma

Quoted 10 lines

drivers/fsi/Ma renamed from drivers/fsi/Makefile +10 -0

+       return FSI_MAX_CASCADE - 1;
+}
+
+/*
+ * Build a mask where bit index 'x' is set (numbering from left to right.
+ * Bit 0 is MSB and bit 31 is LSM.
+ */
+static inline unsigned long mask32(int x)
+{
+       return 1 << (BITS_PER_LONG - x - 1);

Is this masking in IBM bit ordering?

Quoted 2 lines

We should pull the macros (or at least copy them) from arch/powerpc so we can use them here.

Will do, should be easy

Quoted 53 lines

Quoted 53 lines

drivers/fsi/Ma renamed from drivers/fsi/Makefile +14 -0

+}
+
+/*
+ * Various function prototypes
+ */
+int slv_install(void);
+void slv_uninstall(void);
+
+void fsi_exit_fileio(dev_t);
+
+int fsibus_init(void);
+void fsibus_exit(void);
+
+#endif /* DRIVERS_FSI_PRIVATE_H */

drivers/fsi/fsicfam.h new file +32 -0

new file mode 100644
index 0000000..dde7036
@@ -0,0 +1,46 @@
+/*
+ * FSI CFAM structure definitions and defines
+ *
+ * Copyright 2016 IBM Corp.
+ *
+ * Christopher Bostic <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+#ifndef DRIVERS_FSICFAM_H
+#define DRIVERS_FSICFAM_H
+
+#include "fsi.h"
+#include "fsi_private.h"
+
+#define FSI_MAX_ENGINES                32      /* Max # of engines per CFAM */
+
+struct fsicfam {                       /* CFAM internal structure */
+       struct fsidevice *engines[FSI_MAX_ENGINES];     /* CFAM engine data */
+       u32 cfgtab[FSI_MAX_ENGINES];    /* Configuration word */
+       u16 chipid;                     /* CFAM chip type (IOU, CFAM-S, etc) */
+       u8 id;                          /* CFAM Id */
+       bool has_submaster;             /* CFAM with cascaded or hub masters */
+       bool has_mux;                   /* CFAM with multiplexer */
+       u8 ec_maj;                      /* Major EC Level */
+       u8 ec_min;                      /* Minor EC Level or version number */
+       u16 pages;                      /* # Mapped pages */
+       u8 no_eng;                      /* Number of engines[] */
+       struct fsidevice fsidev;        /* LDM entry */

Quoted 8 lines

drivers/fsi/fsicfam.h line 38

Quoted 6 lines

drivers/fsi/fsicfam.h new file +6 -0

+       struct fsidevice hpdone;        /* Dummy engine to signal completion */
+       unsigned long eng_build;        /* True during engine activate */
+       struct fsimaster *master;       /* pointer to parent master */
+};
+
+#define to_fsicfam(x)  container_of((x), struct fsicfam, fsidev)

Make this a function.

Will change.

Quoted 48 lines

Quoted 36 lines

drivers/fsi/fsicfam.h new file +8 -0

+
+/*
+ * CFAM specific function prototypes.
+ */
+int fsi_cfamirq_request(int, struct fsicfam *);
+void fsi_cfamirq_free(struct fsicfam *);
+
+#endif /* DRIVERS_FSICFAM_H */

drivers/fsi/fsiinit.c +2 -0

index 767c0c3..c589294 100644
@@ -13,7 +13,9 @@
 
 #include <linux/init.h>
 #include <linux/module.h>
+#include <linux/kdev_t.h>
 #include "fsiinit.h"
+#include "fsimaster.h"
 
 MODULE_AUTHOR("Christopher Bostic [email protected]");
 MODULE_DESCRIPTION("FSI master device driver");

@@ -26,6 +28,7 @@ MODULE_DESCRIPTION("FSI master device driver");

struct fsidd fsidd = { /* FSI device driver structure definition */
.magic = FSI_DD_MAGIC,
.strno = FSI_DD_STRNO,
+ .major = MKDEV(FSIDD_MAJOR, 0),
};

static int fsi_start(void)

drivers/fsi/fsiinit.c +1 -0

@@ -33,6 +36,25 @@ static int fsi_start(void)
       int rc = 0;
 
       dev_dbg(&fsidd.dev, "FSI DD v:%d installation ok\n", FSIDD_VERNO);
+

drivers/fsi/fsiinit.c static int fsi_start(void) · line 49

Quoted 10 lines

drivers/fsi/fsiinit.c +10 -0

+       init_waitqueue_head(&fsidd.error_wq);
+       init_waitqueue_head(&fsidd.lbus_wq);
+       init_waitqueue_head(&fsidd.irq_wq);
+       init_waitqueue_head(&fsidd.link_wq);
+
+       /*
+        * Initialize the the master
+        */
+       if (!fsimaster_build_init(&fsidd.pri_master, FSI_PRIM, 0)) {
+               rc = PTR_ERR(0);

???

Quoted 12 lines

drivers/fsi/fsiinit.c static int fsi_start(void) · line 58

Quoted 10 lines

drivers/fsi/fsiinit.c +8 -0

+               goto err;
+       }
+       fsimaster_start(&fsidd.pri_master);
+       dev_dbg(&fsidd.dev, "FSI DD v%d installation ok\n", FSIDD_VERNO);
+       return rc;
+
+err:
+       dev_dbg(&fsidd.dev, "FSI DD v:%d installation failed\n", FSIDD_VERNO);
       return rc;

Your formatting is broken.

How is it broken? Not sure what '???' means.

Quoted 68 lines

Quoted 68 lines

drivers/fsi/fsiinit.c +0 -0

 }
 

drivers/fsi/fsiinit.h +2 -0

index 93662533..10ddfc0 100644
@@ -19,6 +19,7 @@
 #include <linux/device.h>
 #include <linux/workqueue.h>
 #include <linux/hrtimer.h>
+#include "fsimaster.h"
 
 #define FSI_DD_MAGIC   0x64644632      /* ddF2 */
 #define FSI_DD_STRNO   0x1             /* Structure version number */

@@ -34,6 +35,7 @@ struct fsidd {                                /* FSI Main structure */
       wait_queue_head_t link_wq;      /* Wait queue for link changes */
       unsigned long state;            /* State driver is in */
       struct device dev;              /* Anchor point in /sys/kernel */
+       struct fsimaster pri_master;    /* Primary FSI master */
 };
 
 #define        to_fsidd_prim(a)        container_of(a, struct fsidd, pri_master)

drivers/fsi/fsimaster.c new file +38 -0

new file mode 100644
index 0000000..b5d16db
@@ -0,0 +1,242 @@
+/*
+ * FSI Master Control
+ *
+ * Copyright 2016 IBM Corp.
+ *
+ * Christopher Bostic <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#include <linux/err.h>
+#include <linux/delay.h>
+#include <linux/ktime.h>
+#include <linux/io.h>
+#include "fsi.h"
+#include "fsiinit.h"
+#include "fsimaster.h"
+#include "fsicfam.h"
+
+static int hpinfo_alloc(struct fsimaster *master)
+{
+       return 0;
+}
+
+static inline unsigned int fsimid(struct fsimaster *master)
+{
+       return master->myid;
+}
+
+static void primaster_exit(struct fsimaster *master)
+{
+       if (master->dcr_alloc) {
+               master->base = NULL;
+               master->dcr_alloc = false;
+       }

Quoted 8 lines

drivers/fsi/fsimaster.c line 44

Quoted 6 lines

drivers/fsi/fsimaster.c new file +6 -0

+}
+
+/*
+ * Read/write functions to access primary FSI master registers
+ * Note that this master is virtual as we don't yet have any
+ * real FSI masters implemented in hardware

"virtual"? What's the purpose of this code?

For implementations without a real hardware FSI master such as soft FSI there is a 'virtual' master in memory where registers are just u32 variables in a data structure. Will add comments to make this clear.

Quoted 15 lines

Quoted 15 lines

drivers/fsi/fsimaster.c new file +14 -0

+ */
+static u32 virt_master_readreg(struct fsi_mreg *mbase, int regnm)
+{
+       u32 *base = (u32 *)mbase;
+
+       return *(base + regnm);
+}
+
+static void virt_master_readreg2(struct fsi_mreg *mbase, int regnm, u64 *dest)
+{
+       u32 *base = (u32 *)mbase;
+
+       memcpy(dest, base + regnm, sizeof(u64));
+}

Quoted 8 lines

drivers/fsi/fsimaster.c line 65

Quoted 8 lines

drivers/fsi/fsimaster.c new file +7 -0

+
+static void virt_master_readreg4(struct fsi_mreg *mbase, int regnm, u32 *dest)
+{
+       u32 *base = (u32 *)mbase;
+
+       memcpy(dest, base + regnm, 4 * sizeof(u32));
+}

_______________________________________________
openbmc mailing list
[email protected]
https://lists.ozlabs.org/listinfo/openbmc

Quoted 113 lines

+++ b/drivers/fsi/fsi.h

drivers/fsi/fsi.h new file +32 -0

@@ -0,0 +1,32 @@
+/*
+ * FSI device driver structure definitions and defines
+ *
+ * Copyright 2016 IBM Corp.
+ *
+ * Christopher Bostic <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+#ifndef DRIVERS_FSI_H
+#define DRIVERS_FSI_H
+
+#include <linux/device.h>
+
+struct fsimap {
+       u8 link;                        /* Master link # */
+       u8 cfam;                        /* CFAM # on link */
+       u32 offset;                     /* Address offset into CFAM */
+       u32 va;                         /* Virtual address */
+};
+
+struct fsidevice {
+       u32 irq_start;                  /* IRQ Number */
+       struct fsidevice *parent;       /* Parent of this device */
+       struct device dev;              /* LDM entry for bus */
+       struct fsimap map;              /* Address & location info */
+};
+
+#endif /* DRIVERS_FSI_H */

drivers/fsi/fsi_private.h new file +73 -0

new file mode 100644
index 0000000..be327ef
@@ -0,0 +1,97 @@
+/*
+ * FSI device driver structure definitions and defines
+ *
+ * Copyright 2016 IBM Corp.
+ *
+ * Christopher Bostic <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+#ifndef DRIVERS_FSI_PRIVATE_H
+#define DRIVERS_FSI_PRIVATE_H
+
+#include "fsi.h"
+
+#define FSIDD_NAME             "fsi"           /* FSI device driver name */
+
+/*
+ * Universal FSI constants - Applicable for any FSI device
+ */
+#define        FSI_MAX_LINKS           64              /* FSI Master # of links */
+#define        FSI_MAX_CASCADE         4               /* # of CFAMS in cascade */
+#define        FSI_MAX_MASTERS         1               /* # of masters in system */
+#define        FSI_LINK_ENG_MASK       0xE0007FFF      /* Used for minor num calcs */
+#define        FSI_MAX_DEPTH           3               /* Max # of links in path */
+#define        FSI_LINK_SHIFT          23                      /* Bits to shift */
+#define        FSI_LINK_SIZE           (1 << FSI_LINK_SHIFT)   /* 8 MB */
+#define        FSI_CFAM_SHIFT          21                      /* Bits to shift */
+#define        FSI_CFAM_SIZE           (1 << FSI_CFAM_SHIFT)   /* 2 MB */
+#define        FSI_ENGINE_SHIFT        10                      /* Bits to shift */
+#define        FSI_ENGINE_SIZE         (1 << FSI_ENGINE_SHIFT) /* 1 KB */
+#define        FSI_LINK_MASK           0x1f800000              /* Bits for link */
+#define        FSI_CFAM_MASK           0x00600000              /* Bits for cfam */
+#define        FSI_ENGINE_MASK         0x000ffc00              /* Bits for engine */
+#define        FSI_PEEK_OFFSET         FSI_ENGINE_SIZE
+#define        FSI_SLAVE0_OFFSET       (2 * FSI_ENGINE_SIZE)
+#define        FSI_SLV_NO_ERROR        100             /* Slave has no error data */
+#define        FSI_BREAK               0xc0de0000      /* BREAK command */
+#define        FSI_TERM                0xecc00000      /* TERM command */
+#define        FSI_BREAK_TIME          180             /* # Seconds to allow BREAKs */
+#define        FSI_BREAK_CNT           3               /* limit for BREAK attempts */
+#define        FSI_PRIM                0               /* Generic Primary FSI master */
+#define        FSI_MBIT_MASK           0x3             /* FSI master  bits in pa */
+#define        FSI_ENG_MASK            0x00007FFF      /* The engine mask in MATRB */
+/* FSI Events */
+#define FSI_EVT_PLUG           6               /* Device plugged */
+#define FSI_LINK_BUILD         10              /* In build up phase */
+#define FSI_LINK_PROBE         11              /* In probing phase */
+
+/*
+ * Return the link number where this device is attached
+ */
+static inline int fsi_my_link(struct fsidevice *fdev)
+{
+       return fdev->map.link;
+}
+
+/*
+ * Return CFAM number on link where this device is attached
+ */
+static inline int fsi_my_cfam(struct fsidevice *fdev)
+{
+       return fdev->map.cfam;
+}
+
+/*
+ * Determine the link address to send the break command to
+ * This is master dependent
+ */
+static inline int fsi_mtype_2break_id(u8 mtype)
+{

drivers/fsi/fsi_private.h line 83

Quoted 10 lines

drivers/fsi/fsi_private.h new file +10 -0

+       return FSI_MAX_CASCADE - 1;
+}
+
+/*
+ * Build a mask where bit index 'x' is set (numbering from left to right.
+ * Bit 0 is MSB and bit 31 is LSM.
+ */
+static inline unsigned long mask32(int x)
+{
+       return 1 << (BITS_PER_LONG - x - 1);

Is this masking in IBM bit ordering?

We should pull the macros (or at least copy them) from arch/powerpc so we can use them here.

Quoted 52 lines

drivers/fsi/fsi_private.h new file +14 -0

+}
+
+/*
+ * Various function prototypes
+ */
+int slv_install(void);
+void slv_uninstall(void);
+
+void fsi_exit_fileio(dev_t);
+
+int fsibus_init(void);
+void fsibus_exit(void);
+
+#endif /* DRIVERS_FSI_PRIVATE_H */

drivers/fsi/fsicfam.h new file +32 -0

new file mode 100644
index 0000000..dde7036
@@ -0,0 +1,46 @@
+/*
+ * FSI CFAM structure definitions and defines
+ *
+ * Copyright 2016 IBM Corp.
+ *
+ * Christopher Bostic <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+#ifndef DRIVERS_FSICFAM_H
+#define DRIVERS_FSICFAM_H
+
+#include "fsi.h"
+#include "fsi_private.h"
+
+#define FSI_MAX_ENGINES                32      /* Max # of engines per CFAM */
+
+struct fsicfam {                       /* CFAM internal structure */
+       struct fsidevice *engines[FSI_MAX_ENGINES];     /* CFAM engine data */
+       u32 cfgtab[FSI_MAX_ENGINES];    /* Configuration word */
+       u16 chipid;                     /* CFAM chip type (IOU, CFAM-S, etc) */
+       u8 id;                          /* CFAM Id */
+       bool has_submaster;             /* CFAM with cascaded or hub masters */
+       bool has_mux;                   /* CFAM with multiplexer */
+       u8 ec_maj;                      /* Major EC Level */
+       u8 ec_min;                      /* Minor EC Level or version number */
+       u16 pages;                      /* # Mapped pages */
+       u8 no_eng;                      /* Number of engines[] */
+       struct fsidevice fsidev;        /* LDM entry */

drivers/fsi/fsicfam.h line 38

Quoted 6 lines

drivers/fsi/fsicfam.h new file +6 -0

+       struct fsidevice hpdone;        /* Dummy engine to signal completion */
+       unsigned long eng_build;        /* True during engine activate */
+       struct fsimaster *master;       /* pointer to parent master */
+};
+
+#define to_fsicfam(x)  container_of((x), struct fsicfam, fsidev)

Make this a function.

Quoted 116 lines · On Thu, Aug 25, 2016 at 5:24 AM, <[email protected]> wrote:

From: Chris Bostic <[email protected]>

Add function to allow the primary FSI master to begin a buildup of a link when a target device is found. Buildup is the process of creating an internal device tree representing the physical target device connections on a given master. First a master must create a link structure and initialize it when there is a target device present on the other end of the link.

Begin process of 'pinging' target device called a 'CFAM'. CFAM (Common Field replaceable unit Access Macro) contains an FSI slave that is the target of any FSI master communications. First the master pings by sending a BREAK command to determine if anyone is listening. If CFAM is accessible by reading its configuration space then the link buildup process begins.

Signed-off-by Chris Bostic <[email protected]>

---
 drivers/fsi/Makefile      |   2 +-
 drivers/fsi/build.c       | 114 +++++++++++++
 drivers/fsi/fsi.h         |  20 +++
 drivers/fsi/fsi_private.h |  21 +++
 drivers/fsi/fsiinit.c     |   3 +
 drivers/fsi/fsilink.h     |  99 ++++++++++++
 drivers/fsi/fsimaster.c   | 218 +++++++++++++++++++++++++
 drivers/fsi/fsimaster.h   |   5 +
 drivers/fsi/fsislave.h    | 404 ++++++++++++++++++++++++++++++++++++++++++++++
 drivers/fsi/ldm.c         |  29 ++++
 drivers/fsi/readwrite.c   |  34 ++++
 11 files changed, 948 insertions(+), 1 deletion(-)
 create mode 100644 drivers/fsi/build.c
 create mode 100644 drivers/fsi/fsilink.h
 create mode 100644 drivers/fsi/fsislave.h
 create mode 100644 drivers/fsi/ldm.c
 create mode 100644 drivers/fsi/readwrite.c

drivers/fsi/Makefile +1 -1

index 9800c15..2445cee 100644
@@ -2,4 +2,4 @@
 # Makefile for the FSI bus specific drivers.
 #
 
-obj-y          += fsiinit.o fsimaster.o
+obj-y          += fsiinit.o fsimaster.o build.o readwrite.o ldm.o

drivers/fsi/build.c new file +65 -0

new file mode 100644
index 0000000..c9a31c0
@@ -0,0 +1,114 @@
+/*
+ * FSI Link Build up
+ *
+ * Copyright 2016 IBM Corp.
+ *
+ * Christopher Bostic <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+#include <linux/err.h>
+#include <linux/delay.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include "fsi.h"
+#include "fsi_private.h"
+#include "fsimaster.h"
+#include "fsicfam.h"
+#include "fsilink.h"
+
+static void link_release(struct device *devp)
+{
+}
+
+/*
+ * Create a FSI link struct and assign it to the FSI tree
+ */
+static struct fsilink *link_add(struct fsimaster *master, int no)
+{
+       int rc = 0;
+       struct fsilink *link = NULL;
+       int id = 0;
+
+       id = fsi_mtype_2break_id(master->type);
+
+       link = kmalloc(sizeof(struct fsilink), GFP_KERNEL);
+       if (!link)
+               return link;
+
+       dev_set_name(&link->fsidev.dev, "link-%d", no);
+       link->id3_addr = (FSI_MAX_CASCADE - 1) * FSI_CFAM_SIZE;
+       link->master = master;
+       link->linkno = no;
+       link->fsidev.map.va = link->id3_addr;
+       link->fsidev.map.cmtype = master->type;
+       link->fsidev.id.engine_type = FSI_ENGID_LINK;
+       link->fsidev.map.kb = fsimaster_linksz(master) / FSI_ENGINE_SIZE;
+       link->fsidev.irq_start = no * (FSI_MAX_CASCADE * FSI_MAX_ENGINES);
+       link->fsidev.irq_range = FSI_MAX_CASCADE * FSI_MAX_ENGINES;
+       if (!master->fsidev)
+               link->fsidev.dev.parent = 0;
+       else
+               link->fsidev.dev.parent = &master->fsidev->dev;
+       link->fsidev.dev.release = link_release;
+
+       /* stub */
+
+       return link ? : ERR_PTR(rc);
+}
+
+static void linkbuild2(struct fsimaster *master, struct fsilink *link)
+{
+}

drivers/fsi/build.c line 71

Quoted 6 lines

drivers/fsi/build.c new file +6 -0

+
+/*
+ * Return number of CFAMs discovered. If something fails during the build up
+ * process return error reason
+ */
+static int linkbuild1(struct fsimaster *master, int no)

The naming needs to be fixed.

Quoted 113 lines

drivers/fsi/build.c new file +43 -0

+{
+       int i, rc = 0;
+       struct fsilink *link = link_add(master, no);
+
+       if (IS_ERR(link))
+               return PTR_ERR(link);
+
+       /* stub */
+
+       linkbuild2(master, link);
+       i = link->cascade;
+       if (i == 0) {
+
+               /* stub */
+
+               rc = -EIO;
+       } else {
+
+               /* stub */
+       }
+
+       return rc;
+}
+
+/*
+ * Build up a link.  Returns number of CFAMs discovered.
+ */
+int fsi_linkbuild(struct fsimaster *master, int no)
+{
+       int rc;
+       u64 menp;
+
+       menp = fsimaster_read_menp(master);
+       if (menp & mask64(no))
+               return -EEXIST;  /* Already running */
+
+       fsimaster_enable_link(master, no);
+       rc = linkbuild1(master, no);
+       if (rc < 0)
+               fsimaster_disable_link(master, no);
+
+       return rc;
+}

drivers/fsi/fsi.h +20 -0

index f146396..b723208 100644
@@ -15,15 +15,35 @@
 
 #include <linux/device.h>
 
+/*
+ * Engine ID's
+ */
+#define FSI_ENGID_LINK         0xff    /* Link Identifier */
+
+/* Engine ID as it appears in the CFAM configuration table */
+struct fsi_engine_id {
+       u8 match_flags;
+       u8 engine_type;
+       u8 engine_version;
+       u8 engine_vendor;
+};
+
+/* Location information for a FSI device */
 struct fsimap {
        u8 link;                        /* Master link # */
        u8 cfam;                        /* CFAM # on link */
+       u8 eng;                         /* Engine # on CFAM */
+       u8 cmtype;                      /* Type of master upstream */
        u32 offset;                     /* Address offset into CFAM */
        u32 va;                         /* Virtual address */
+       u16 kb;                         /* Size of dev engine space */
+       u16 kb_off;                     /* CFAM config table offset data */
 };
 
 struct fsidevice {
+       struct fsi_engine_id id;        /* Engine type/version */
        u32 irq_start;                  /* IRQ Number */
+       u16 irq_range;                  /* Number of IRQs */
        struct fsidevice *parent;       /* Parent of this device */
        struct device dev;              /* LDM entry for bus */
        struct fsimap map;              /* Address & location info */

drivers/fsi/fsi_private.h +12 -0

index be327ef..afa2553 100644
@@ -44,10 +44,22 @@
 #define        FSI_PRIM                0               /* Generic Primary FSI master */
 #define        FSI_MBIT_MASK           0x3             /* FSI master  bits in pa */
 #define        FSI_ENG_MASK            0x00007FFF      /* The engine mask in MATRB */
+
 /* FSI Events */
+#define FSI_EVT_LBUSLOST       1               /* Local bus loss */
+#define FSI_EVT_LBUSRECV       2               /* Local bus gained */
+#define FSI_EVT_IRQLOOP                3               /* IRQ loop detected */
+#define FSI_EVT_LINKCHG                4               /* Link state change */
+#define FSI_EVT_UNPLUG         5               /* Device unplugged */
 #define FSI_EVT_PLUG           6               /* Device plugged */
+#define FSI_EVT_CFAMADD                7               /* New CFAM found */
+#define FSI_EVT_CFAMDELETE     8               /* Removing a CFAM */
+#define FSI_EVT_CFAMDEAD       9               /* CFAM no longer functions */
 #define FSI_LINK_BUILD         10              /* In build up phase */
 #define FSI_LINK_PROBE         11              /* In probing phase */
+#define FSI_LINK_RUNNING       12              /* Link up and running */
+#define FSI_LINK_DEAD          13              /* Link defective */
+#define FSI_LINK_WAITFOR       14              /* Wait for buildup */
 
 /*
  * Return the link number where this device is attached

@@ -76,6 +88,15 @@ static inline int fsi_mtype_2break_id(u8 mtype)
 

drivers/fsi/fsi_private.h static inline int fsi_mtype_2break_id(u8 mtype) · line 97

Quoted 9 lines

drivers/fsi/fsi_private.h +7 -0

 /*
  * Build a mask where bit index 'x' is set (numbering from left to right.
+ * Bit 0 is MSB and bit 63 is LSM.
+ */
+static inline u64 mask64(int x)
+{
+       return 1 << (BITS_PER_LONG_LONG - x - 1);
+}
+

I've seen this function before. Can we share it?

Quoted 53 lines

drivers/fsi/fsi_private.h +2 -0

+/*
+ * Build a mask where bit index 'x' is set (numbering from left to right.
  * Bit 0 is MSB and bit 31 is LSM.
  */
 static inline unsigned long mask32(int x)

drivers/fsi/fsiinit.c +3 -0

index c589294..eaa3582 100644
@@ -14,8 +14,11 @@
 #include <linux/init.h>
 #include <linux/module.h>
 #include <linux/kdev_t.h>
+#include <linux/io.h>
+#include <linux/slab.h>
 #include "fsiinit.h"
 #include "fsimaster.h"
+#include "fsi_private.h"
 
 MODULE_AUTHOR("Christopher Bostic [email protected]");
 MODULE_DESCRIPTION("FSI master device driver");

drivers/fsi/fsilink.h new file +26 -0

new file mode 100644
index 0000000..f923650
@@ -0,0 +1,99 @@
+/*
+ * FSI link structure definitions and defines
+ *
+ * Copyright 2016 IBM Corp.
+ *
+ * Christopher Bostic <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+#ifndef DRIVERS_FSILINK_H
+#define DRIVERS_FSILINK_H
+
+#include <linux/types.h>
+#include <linux/kobject.h>
+#include <linux/device.h>
+#include "fsi.h"
+#include "fsi_private.h"
+
+/*
+ * Extended FSI error counting and thresholding. Count the FSI errors with
+ * time they occurred.
+ */
+#define        FSI_MAX_PE      6               /* Max # of FSI port errors */

drivers/fsi/fsilink.h line 33

Quoted 7 lines

drivers/fsi/fsilink.h new file +7 -0

+#define        FSI_MAX_ME      11              /* Max # of FSI master errors */
+#define        FSI_MAX_SE      10              /* Max # of FSI slave V3 errors */
+#define        FSI_MAX_SEV2    6               /* Max # of FSI slave V2 errors */
+
+struct fsi_ecnt {                      /* Structure for counting errors */
+       unsigned short cnt;             /* Counter */
+       struct timeval seen_1st;        /* First occurrence */

first

Quoted 12 lines

drivers/fsi/fsilink.h new file +11 -0

+       struct timeval seen_last;       /* Last occurrence */
+};
+
+struct fsi_eport {                     /* Port error statistics */
+       unsigned short pec[FSI_MAX_PE]; /* Port errors counter per type */
+       unsigned short pcrc_cnt;        /* Recovered CRC counter port */
+};
+
+struct fsi_eslv {                      /* Slave error statistics */
+       unsigned short sec[FSI_MAX_SE]; /* Slave errors counter per type  */
+       unsigned short scrc_cnt;        /* Recovered CRC counter slave */

drivers/fsi/fsilink.h line 50

Quoted 6 lines

drivers/fsi/fsilink.h new file +6 -0

+};
+
+struct fsi_emaster {                   /* Master error statistics */
+       unsigned short mec[FSI_MAX_ME]; /* Master errors counter per type */
+       unsigned short mcrc_cnt;        /* Recovered CRC counter master */
+};

Could all of these statistics go in the one struct?

Quoted 69 lines

drivers/fsi/fsilink.h new file +49 -0

+
+struct fsi_elink {                     /* Link error statistics */
+       struct fsi_emaster master;      /* Master errors */
+       struct fsi_eport port;          /* Port errors */
+       struct fsi_eslv slv[FSI_MAX_CASCADE];   /* Slave errors */
+       struct fsi_ecnt breaked;        /* BREAK command sent */
+};
+
+enum fsilink_state {                   /* Bit mask for error states */
+       fsilink_lost = 1,               /* Link already schedule for removal */
+       fsilink_up = 2,                 /* Link up & running */
+       fsilink_going = 3               /* Link removal in progress */
+};
+
+struct fsilink {                       /* Information per link */
+       u8 speedset;                    /* Link speed set (0 or 1) */
+       u8 cascade;                     /* Length of cascade */
+       u8 top_cfam;                    /* # CFAM found on initial scan */
+       u8 linkno;                      /* Number of this link */
+       unsigned long state;            /* Bit mask for error states */
+       struct fsicfam *cfams[FSI_MAX_CASCADE]; /* CFAMs per link */
+       struct fsidevice fsidev;
+       u32 id3_addr;                   /* CFAM id3 page */
+       struct fsimaster *master;       /* Ptr to controlling fsi master */
+       struct fsi_elink error;         /* Errors on this link */
+};
+
+#define FSILINK_ATTR(_name, _mode, _show, _store)      \
+struct device_attribute fsilink_attr_##_name = {       \
+       .attr = {                                       \
+               .name = __stringify(_name),             \
+               .mode = _mode,                          \
+       },                                              \
+       .show   = _show,                                \
+       .store  = _store                                \
+}
+
+/*
+ * Pointer conversion from fsidevice member to fsilink.
+ */
+#define        to_fsilink(x)   container_of((x), struct fsilink, fsidev)
+
+unsigned char fsilink_get_top_cfam(struct fsilink *);
+unsigned char fsilink_get_linkno(struct fsilink *);
+unsigned long fsilink_get_state(struct fsilink *);
+struct fsicfam *fsilink_get_cfam(struct fsilink *, int);
+struct device *fsilink_get_device(struct fsilink *);
+
+#endif /* DRIVERS_FSILINK_H */

drivers/fsi/fsimaster.c +2 -0

index 8054051..427231f 100644
@@ -17,9 +17,11 @@
 #include <linux/io.h>
 #include <linux/bitops.h>
 #include "fsi.h"
+#include "fsi_private.h"
 #include "fsiinit.h"
 #include "fsimaster.h"
 #include "fsicfam.h"
+#include "fsislave.h"
 
 static int hpinfo_alloc(struct fsimaster *master)
 {

@@ -150,6 +152,9 @@ static int fsimaster_init(struct fsimaster *master)
        return rc;
 }
 

drivers/fsi/fsimaster.c static int fsimaster_init(struct fsimaster *master) · line 157

Quoted 3 lines

drivers/fsi/fsimaster.c +3 -0

+/*
+ * Retrieve the first master in the chain
+ */

The comment should be added when you add the function.

Quoted 750 lines

drivers/fsi/fsimaster.c +213 -0

 struct fsimaster *fsimaster_get_top_master(struct fsimaster *master)
 {
        struct fsimaster *parent = NULL;

@@ -163,10 +168,195 @@ struct fsimaster *fsimaster_get_top_master(struct fsimaster *master)
 }
 
 /*
+ * Get the address space size of a link/CFAM
+ */
+
+u32 fsimaster_cfamsz(struct fsimaster *master)
+{
+       return master->cfam_size;
+}
+
+u32 fsimaster_linksz(struct fsimaster *master)
+{
+       return FSI_MAX_CASCADE * fsimaster_cfamsz(master);
+}
+
+/*
+ * Find physical address given master and link #
+ */
+u32 fsimaster_link2pa(struct fsimaster *master, int link)
+{
+       u32 offset = link * fsimaster_linksz(master);
+
+       return master->membase + offset;
+}
+
+/*
+ * Find physical address given master, link # and CFAM #
+ */
+u32 fsimaster_cfam2pa(struct fsimaster *master, int link, int cfam)
+{
+       u32 offset = link * fsimaster_linksz(master) +
+                    cfam * fsimaster_cfamsz(master);
+
+       return master->membase + offset;
+}
+
+int fsim_pa2irq(struct fsimaster *master, u32 pa)
+{
+       return 0;
+}
+
+int fsi_pa2irq(u32 pa)
+{
+       return 0;
+}
+
+/*
+ * Master control register accessors
+ */
+
+/*
+ * Read/write  mode register: MMODE
+ */
+u32 fsimaster_read_mmode_nl(struct fsimaster *master)
+{
+       return master->read_reg(master->base, FSI_N_MMODE);
+}
+
+u32 fsimaster_read_mmode(struct fsimaster *master)
+{
+       return 0;
+}
+
+void fsimaster_write_mmode(struct fsimaster *master, u32 value)
+{
+}
+
+/*
+ * Read/write enable port register: MENP
+ */
+u64 fsimaster_read_menp_nl(struct fsimaster *master)
+{
+       return 0;
+}
+
+u64 fsimaster_read_menp(struct fsimaster *master)
+{
+       return 0;
+}
+
+void fsimaster_write_menp(struct fsimaster *master, u64 *menp, int on_off)
+{
+}
+
+void fsimaster_disable_link(struct fsimaster *master, int link)
+{
+}
+
+void fsimaster_enable_link(struct fsimaster *master, int link)
+{
+}
+
+/*
+ * Send out a BREAK command and see if anything response.  Part of the scan
+ * process
+ */
+static int ping_cfam(struct fsimaster *master, struct fsi_hotplug *hp,
+                    const int count)
+{
+       int i = 0, rc = -EIO;
+       u32 value, pa;
+       int id = fsi_mtype_2break_id(master->type);
+
+       pa = fsimaster_cfam2pa(master, hp->linkno, id);
+
+       fsimaster_enable_link(master, hp->linkno);
+       if (fsi_sendbreak(master, pa, hp->linkno))
+               goto out;
+
+       while (i++ < count) {
+               rc = fsi_readw_int(master, pa + FSI_SLAVE0_OFFSET + FSI_SMODE,
+                                  &value);
+               if (rc == 0)
+                       break;
+
+               udelay(FSI_CFAM_PING_DELAY);
+       }
+out:
+       fsimaster_disable_link(master, hp->linkno);
+
+       return rc;
+}
+
+/*
+ * Probe for CFAMs
+ */
+static int probe_link(struct fsimaster *master, struct fsi_hotplug *hp)
+{
+       int rc = 0;
+       struct fsidd *dd = to_fsidd_prim(fsimaster_get_top_master(master));
+
+       hp->tries++;
+       rc = ping_cfam(master, hp, FSI_MAX_CASCADE - 1);
+       if (rc == 0) {
+               atomic_set(&hp->state, FSI_LINK_BUILD);
+               set_bit(FSI_LINK_BUILD, &dd->state);
+               set_bit(hp->linkno, &master->hotp.building);
+               clear_bit(hp->linkno, &master->hotp.probing);
+               rc = 1;
+       } else if (hp->tries > FSI_MAX_PING_ATTEMPTS) {
+               atomic_set(&hp->state, FSI_EVT_CFAMDEAD);
+               clear_bit(hp->linkno, &master->hotp.probing);
+       }
+
+       return rc;
+}
+
+/*
  * Work queue function to probe links
  */
 static void probe_wq(struct work_struct *work)
 {
+       struct fsimaster *master = to_fsimaster_probe(work);
+       struct fsidd *dd = to_fsidd_prim(fsimaster_get_top_master(master));
+       int i, cnt = 0;
+
+       for (i = 0; i < master->maxlinks; ++i) {
+               if (test_bit(i, &master->hotp.probing))
+                       cnt += probe_link(master, master->hotp.plug[i]);
+       }
+       if (cnt)
+               queue_work(dd->hotp_wq, &master->hotp.buildwork);
+}
+
+/*
+ * Called from worker in process/task context
+ */
+static int build(struct fsimaster *master, struct fsi_hotplug *hp)
+{
+       int rc;
+
+       rc = fsi_linkbuild(master, hp->linkno);
+       atomic_set(&hp->state, rc ? FSI_LINK_RUNNING : FSI_LINK_DEAD);
+       if (test_and_clear_bit(FSI_LINK_WAITFOR, &hp->wait_state))
+               complete_all(&hp->done);
+
+       return rc;
+}
+
+static int remove(struct fsimaster *master, struct fsi_hotplug *hp)
+{
+       return 0;
+}
+
+/*
+ * Actual link build function.  Called in process context.
+ */
+static void build_link(struct fsimaster *master, struct fsi_hotplug *hp)
+{
+       hp->error_code = (hp->cmd == FSI_EVT_CFAMADD) ? build(master, hp)
+                                                    : remove(master, hp);
 }
 
 /*

@@ -174,6 +364,34 @@ static void probe_wq(struct work_struct *work)
  */
 static void build_wq(struct work_struct *work)
 {
+       struct fsimaster *master = to_fsimaster_build(work);
+       struct fsidd *dd = to_fsidd_prim(fsimaster_get_top_master(master));
+       int i;
+
+       set_bit(FSI_LINK_BUILD, &dd->state);
+again:
+       for (i = 0; i < master->maxlinks; ++i) {
+               if (test_and_clear_bit(i, &master->hotp.building))
+                       build_link(master, master->hotp.plug[i]);
+       }
+
+       /* stub */
+
+       /*
+        * Make sure all bits were cleared before leaving.
+        * This worker runs in process context.  While running, an FSI error
+        * interrupt can occur and schedule a link for removal.
+        * If we are past this new bit in our loop above, the link is not
+        * removed.  Iterate on non zero.
+        */
+       if (master->hotp.building)
+               goto again;
+
+       /*
+        * If the same described above happens here, we are toast again.
+        * Another perodic check is done on plugmgr()
+        */
+       clear_bit(FSI_LINK_BUILD, &dd->state);
 }
 
 static int fsimaster_reset(struct fsimaster *master)

drivers/fsi/fsimaster.h +5 -0

index 61e8c8a..0d47dc6 100644
@@ -20,6 +20,7 @@
 #define FSI_MAX_PING_ATTEMPTS  12
 #define        FSI_PLUG_CHECK_TIME     100
 #define FSI_DFLT_IPOLL_CHECK   800
+#define FSI_CFAM_PING_DELAY    20      /* in microseconds */
 
 /* FSI master register numbers */
 #define        FSI_N_MMODE     0       /* 0x0   R/W: mode register */

@@ -524,6 +525,7 @@ struct fsi_hotplug {                        /* Hot plug information */
        struct completion done;         /* Link build done */
        u16 tries;                      /* # of tries before probing */
        u8 linkno;                      /* Link # */
+       u8 cmd;                         /* State add/delete */
        atomic_t state;                 /* State of this entry */
        int error_code;                 /* Error code */
        unsigned long wait_state;       /* Wait state */

@@ -673,4 +675,7 @@ void fsimaster_engput(struct fsidevice *);
 void fsi_rst_error2(struct fsimaster *, struct fsidevice *, int, int, int, int);
 int port_reset(struct fsimaster *, int);
 
+int fsi_writew_int(struct fsimaster *, u32, u32);
+int fsi_readw_int(struct fsimaster *, u32, u32*);
+
 #endif /* DRIVERS_FSIMASTER_H */

drivers/fsi/fsislave.h new file +404 -0

new file mode 100644
index 0000000..f2095d3
@@ -0,0 +1,404 @@
+/*
+ * FSI slave structure definitions and defines
+ *
+ * Copyright 2016 IBM Corp.
+ *
+ * Christopher Bostic <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+#ifndef        DRIVERS_FSISLAVE_H
+#define        DRIVERS_FSISLAVE_H
+
+/*
+ * Define read address for peek engine referring to
+ * side/series/node-id/frame-id
+ */
+#define FSI_PEEK_IDADDR        0xc
+
+#define FSI_SLV_CFAM_OFFSET 0x800
+
+/*
+ * Defines for address locations of certain register in FSI Slave. All register
+ * names start with FSI_S for slave register. Some registers have the
+ * same address but different meanings for read and write access.
+ */
+#define        FSI_SMODE       0x0     /* R/W: Slave mode register */
+#define        FSI_SDMA        0x4     /* R/W: DMA control register */
+#define        FSI_SISC        0x8     /* Read: read Interrupt condition register */
+#define        FSI_SCISC       0x8     /* Write: Clear Interrupt condition register */
+#define        FSI_SISM        0xC     /* R/W: Interrupt mask register */
+#define        FSI_SISS        0x10    /* Read: Interrupt status register */
+#define        FSI_SSISM       0x10    /* Write: Set interrupt mask */
+#define        FSI_SSTAT       0x14    /* Read: Read slave status register */
+#define        FSI_SCISM       0x14    /* Write: Clear interrupt mask */
+#define        FSI_SI1M        0x18    /* R/W: Interrupt 1 mask register */
+#define        FSI_SI1S        0x1C    /* Read: Read Interrupt 1 status register */
+#define        FSI_SSI1M       0x1C    /* Write: Set Interrupt 1 mask register */
+#define        FSI_SIC         0x20    /* Read: Read engine interrupt condition reg */
+#define        FSI_SCI1M       0x20    /* Write: Clear Interrupt 1 mask register */
+#define        FSI_SI2M        0x24    /* R/W: Interrupt 2 mask register */
+#define        FSI_SI2S        0x28    /* Read: Read Interrupt 2 status register */
+#define        FSI_SSI2M       0x28    /* Write: Set Interrupt 2 mask register */
+#define        FSI_SCMDT       0x2C    /* Read: Command trace register */
+#define        FSI_SCI2M       0x2C    /* Write: Clear Interrupt 2 mask register */
+#define        FSI_SDATAT      0x30    /* Read: Data trace register */
+#define        FSI_SLBUS       0x30    /* Write: local bus address commands */
+#define        FSI_SLASTD      0x34    /* Read: Last data send register */
+#define        FSI_SRES        0x34    /* Write: Reset command register */
+#define        FSI_SMBL        0x38    /* R/W: Mailbox register left port */
+#define        FSI_SOML        0x3C    /* Read: Mailbox old data register left port */
+#define        FSI_SSMBL       0x3C    /* Write: Set Mailbox bits register left port */
+#define        FSI_SNML        0x40    /* Read: Mailbox new data register left port */
+#define        FSI_SCMBL       0x40    /* Write: Clear mailbox bits left port */
+#define FSI_SMBR       0x44    /* R/W: Mailbox register right port */
+#define FSI_SOMR       0x48    /* Read: Mailbox old data register right port */
+#define FSI_SSMBR      0x48    /* Write: Set Mailbox bits register right port*/
+#define FSI_SNMR       0x4c    /* Read: Mailbox new data register right port */
+#define FSI_SCMBR      0x4c    /* Write: Clear mailbox bits right port */
+
+/* Same as above except Word offsets into the FSI slave engine */
+#define FSI_N_SISC     0x2     /* Read: read Interrupt condition register */
+#define FSI_N_SSTAT    0x5     /* Read: Slave Status register */
+#define FSI_N_SCMDT    0xB     /* Read: Command trace register */
+#define FSI_N_SDATAT   0xC     /* Read: Data trace register */
+#define FSI_N_SLASTD   0xD     /* Read: Last data send register */
+
+/* Next registers are only valid for FSI slave version 3 */
+#define FSI_SRSIC      0x50    /* Read slave remote slave IRQ condition */
+#define FSI_SCRSIC     0x50    /* Write: Clear Slave remote slave IRQ cond */
+#define FSI_SRSIM      0x54    /* R/W: Slave remote slave IRQ mask */
+#define FSI_SRSIS      0x58    /* Read: Slave remote slave IRQ status */
+
+/* Next registers are only valid for FSI slave version 4 */
+/* cmFSI */
+#define FSI_ScRSIC0    0x50    /* Read / Write: to clear cmFSI remote */
+/* slave IRQ condition ports 0-3 */
+#define FSI_ScRSIC4    0x54    /* Read / Write: to clear cmFSI remote */
+/* slave IRQ condition ports 4-7 */
+#define FSI_ScRSIM0    0x58    /* R/W: cmFSI remote slave IRQ mask */
+/* ports 0-3 */
+#define FSI_ScRSIM4    0x5C    /* R/W: cmFSI remote slave IRQ mask */
+/* ports 4-7 */
+#define FSI_ScRSIS0    0x60    /* Read: cmFSI remote slave IRQ status */
+/* ports 0-3 */
+#define FSI_ScRSIS4    0x64    /* Read: cMFSI remote slave IRQ status */
+/* ports 4-7 */
+/* hFSI */
+#define FSI_SRSIC0     0x68    /* Read / Write: to clear hFSI remote */
+/* slave IRQ condition ports 0-3 */
+#define FSI_SRSIC4     0x6C    /* Read / Write: to clear hFSI remote */
+/* slave IRQ condition ports 4-7 */
+#define FSI_SRSIM0     0x70    /* R/W: hFSI remote slave IRQ mask */
+/* ports 0-3 */
+#define FSI_SRSIM4     0x74    /* R/W: hFSI remote slave IRQ mask */
+/* ports 4-7 */
+#define FSI_SRSIS0     0x78    /* Read: hFSI remote slave IRQ status */
+/* ports 0-3 */
+#define FSI_SRSIS4     0x7C    /* Read: hFSI remote slave IRQ status */
+/* ports 4-7 */
+
+#define FSI_SRSIM_SID3_SHIFT   6
+
+/* Slave ID 3 on interrupt level 1 for all sub/hub links */
+#define SRSIM_ID3_IRPT1_MASK   0x02020202
+#define SRSIM_MAGIC            SRSIM_ID3_IRPT1_MASK
+
+struct fsi_sreg {              /* FSI slave register definition */
+       u32 smode;              /* 0x0: Mode register */
+       u32 sdma;               /* 0x4: DMA control register */
+       u32 sisc;               /* 0x8: Slave interrupt condition register */
+       u32 sism;               /* 0xc: Slave interrupt mask register */
+       u32 siss;               /* 0x10: Slave interrupt status register */
+       u32 sstat;              /* 0x14: Slave status register */
+       u32 si1m;               /* 0x18: interrupt 1 mask register */
+       u32 si1s;               /* 0x1c: interrupt 1 status register */
+       u32 sic;                /* 0x20: engine interrupt condition register */
+       u32 si2m;               /* 0x24: interrupt 2 mask register */
+       u32 si2s;               /* 0x28: interrupt 2 status register */
+       u32 scmdt;              /* 0x2c: read command trace register */
+       u32 sdatat;             /* 0x30: read data trace register */
+       u32 slastd;             /* 0x34: read last FSI data register */
+       u32 smbl;               /* 0x38: mail box to left port register */
+       u32 soml;               /* 0x3c: old mail left port register */
+       u32 snml;               /* 0x40: new mail left port register */
+       u32 smbr;               /* 0x44: mail box to right port register */
+       u32 somr;               /* 0x48: old mail right port register */
+       u32 snmr;               /* 0x4c: new mail right port register */
+       u32 srsic0;             /* 0x50: slave remote slave IRQ cond. 0-3 */
+       u32 srsic4;             /* 0x54: slave remote slave IRQ cond. 4-7 */
+       u32 srsim0;             /* 0x58: slave remote slave IRQ mask 0-3 */
+       u32 srsim4;             /* 0x5C: slave remote slave IRQ mask 4-7 */
+       u32 srsis0;             /* 0x60: slave remote slave IRQ stat 0-3 */
+       u32 srsis4;             /* 0x64: slave remote slave IRQ stat 4-7 */
+};
+
+/*
+ * FSI slave mode register
+ */
+#define        FSI_SMODE_WSC           0x80000000      /* Warm start completed */
+#define        FSI_SMODE_EAP           0x40000000      /* Enable auxiliary port */
+#define        FSI_SMODE_ECRC          0x20000000      /* Enable CRC checking by hw */
+#define        FSI_SMODE_SID_SHIFT     24              /* Slave identifier shift */
+#define        FSI_SMODE_SID_MASK      3               /* Slave identifier mask */
+#define        FSI_SMODE_ED_SHIFT      20              /* Echo delay cycles shift */
+#define        FSI_SMODE_ED_MASK       0xf             /* Echo delay cycles mask */
+#define        FSI_SMODE_SD_SHIFT      16              /* Send delay cycles shift */
+#define        FSI_SMODE_SD_MASK       0xf             /* Send delay cycles mask */
+#define        FSI_SMODE_LBCRR_SHIFT   8               /* Local bus clk rate shift */
+#define        FSI_SMODE_LBCRR_MASK    0xf             /* Local bus clk rate mask */
+#define        FSI_SMODE_BDL_SHIFT     4               /* Briefing data left shift */
+#define        FSI_SMODE_BDL_MASK      0xf             /* Briefing data mask */
+#define        FSI_SMODE_BDR_SHIFT     0               /* Briefing data right shift */
+#define        FSI_SMODE_BDR_MASK      0xf             /* Briefing data mask */
+#define        FSI_SMODE_RSV_MASK      0xe3ff0fff      /* Mask for used bit clr rsvd */
+
+/* FSI slave local bus echo delay */
+static inline u32 fsi_smode_echodly(int x)
+{
+       return (x & FSI_SMODE_ED_MASK) << FSI_SMODE_ED_SHIFT;
+}
+
+/* FSI slave local bus send delay */
+static inline u32 fsi_smode_senddly(int x)
+{
+       return (x & FSI_SMODE_SD_MASK) << FSI_SMODE_SD_SHIFT;
+}
+
+/* FSI slave local bus clock rate ratio */
+static inline int fsi_smode_extlbcrr(u32 x)
+{
+       return (x >> FSI_SMODE_LBCRR_SHIFT) & FSI_SMODE_LBCRR_MASK;
+}
+
+/* FSI slave local bus clock rate ratio */
+static inline u32 fsi_smode_lbcrr(int x)
+{
+       return (x & FSI_SMODE_LBCRR_MASK) << FSI_SMODE_LBCRR_SHIFT;
+}
+
+/* FSI slave identifier setting */
+static inline u32 fsi_smode_sid(int x)
+{
+       return (x & FSI_SMODE_SID_MASK) << FSI_SMODE_SID_SHIFT;
+}
+
+/* FSI slave briefing data right port */
+static inline u32 fsi_smode_bdr(int x)
+{
+       return (x & FSI_SMODE_BDR_MASK) << FSI_SMODE_BDR_SHIFT;
+}
+
+static inline int fsi_smode_extbdr(u32 x)
+{
+       return (x >> FSI_SMODE_BDR_SHIFT) & FSI_SMODE_BDR_MASK;
+}
+
+/* FSI slave briefing data left port */
+static inline u32 fsi_smode_bdl(int x)
+{
+       return (x & FSI_SMODE_BDL_MASK) << FSI_SMODE_BDL_SHIFT;
+}
+
+static inline int fsi_smode_extbdl(u32 x)
+{
+       return (x >> FSI_SMODE_BDL_SHIFT) & FSI_SMODE_BDL_MASK;
+}
+
+/* FSI slave echo delay */
+static inline u32 fsi_smode_ed(int x)
+{
+       return (x & FSI_SMODE_ED_MASK) << FSI_SMODE_ED_SHIFT;
+}
+
+static inline int fsi_smode_exted(u32 x)
+{
+       return (x >> FSI_SMODE_ED_SHIFT) & FSI_SMODE_ED_MASK;
+}
+
+/* FSI slave send delay */
+static inline u32 fsi_smode_sd(int x)
+{
+       return (x & FSI_SMODE_SD_MASK) << FSI_SMODE_SD_SHIFT;
+}
+
+static inline int fsi_smode_extsd(u32 x)
+{
+       return (x >> FSI_SMODE_SD_SHIFT) & FSI_SMODE_SD_MASK;
+}
+
+/*
+ * FSI slave interrupt register: interrupt conditions, status and mask
+ */
+#define        FSI_SSI_CRCE            0x80000000      /* FSI CRC error */
+#define        FSI_SSI_PROTE           0x40000000      /* FSI protocol error */
+#define        FSI_SSI_LBPE            0x20000000      /* FSI local bus parity error */
+#define        FSI_SSI_LBPROTE         0x10000000      /* FSI local bus protocol err */
+#define        FSI_SSI_LBAE            0x08000000      /* FSI local bus access error */
+#define        FSI_SSI_LBOE            0x04000000      /* FSI local bus owner error */
+#define        FSI_SSI_LBOC            0x02000000      /* FSI local bus owner change */
+#define        FSI_SSI_HPE             0x01000000      /* Hot plug event */
+#define        FSI_SSI_MRL             0x00800000      /* Mail received left port */
+#define        FSI_SSI_MDL             0x00400000      /* Mail send left port */
+#define        FSI_SSI_WSL             0x00200000      /* Warm start flag left port */
+#define        FSI_SSI_LBRL            0x00100000      /* Local bus requ left port */
+#define        FSI_SSI_MRR             0x00080000      /* Mail received right port */
+#define        FSI_SSI_MDR             0x00040000      /* Mail delivered right port */
+#define        FSI_SSI_WSR             0x00020000      /* Warm start flag right port */
+#define        FSI_SSI_LBRR            0x00010000      /* Local bus req right port */
+#define        FSI_SSI_CMEL            0x00008000      /* Clocks monitor event left */
+#define        FSI_SSI_CMER            0x00004000      /* Clocks monitor event right */
+#define        FSI_SSI_OPB_FNC         0x00001000      /* OPB Fenced (cMFSI & hMFSI) */
+#define        FSI_SSI_OBP_PA          0x00000800      /* OPB Parity (cMFSI) */
+#define        FSI_SSI_OBP_PR          0x00000400      /* OPB Protocol (cMFSI) */
+#define        FSI_SSI_OBP_TO          0x00000200      /* OPB Timeout (cMFSI) */
+#define        FSI_SSI_OBP_EA          0x00000100      /* OPB ErrorAck (cMFSI) */
+#define        FSI_SSI_OBP_IA          0x00002000      /* OPB Invalid Address (cMFSI)*/
+#define        FSI_SSI_CMFSI_AME       0x00000080      /* CMFSI any-master-error */
+#define        FSI_SSI_CMFSI_APE       0x00000040      /* CMFSI any-port-error */
+#define        FSI_SSI_CMFSI_HPE       0x00000020      /* CMFSI Hot plug event */
+#define        FSI_SSI_CMFSI_CRPA      0x00000010      /* CMFSI Contr reg parity err */
+#define        FSI_SSI_ANY_IRQ         0xffffc000      /* Valid bits */
+#define        FSI_SSI_ANY_IRQ3        (FSI_SSI_CMFSI_AME | FSI_SSI_CMFSI_APE \
+                               | FSI_SSI_CMFSI_HPE | FSI_SSI_CMFSI_CRPA)
+                                               /* Valid bits (cMFSI) */
+#define        FSI_SSI_ANY_ERROR       0xfc000000      /* Valid error bits */
+#define        FSI_SSI_ANY_ERROR3      (FSI_SSI_OBP_PA \
+                               | FSI_SSI_OBP_PR | FSI_SSI_OBP_TO \
+                               | FSI_SSI_OBP_EA | FSI_SSI_OBP_IA)
+                                               /* Valid error bits (cMFSI) */
+#define        FSI_SSI_ERR_MASK        0x3f            /* Any error bits mask */
+#define        FSI_SSI_ERR_SHFT        26              /* Any error bits shift */
+#define        FSI_SISC_CRCE           0               /* Slave CRC error bit */
+#define        FSI_SISC_PE             1               /* Slave protocol error bit */
+#define        FSI_SISC_LBPE           2               /* Slave lcl bus parity err */
+#define        FSI_SISC_LBPROTOE       3               /* Slave lcl bus prot err */
+#define        FSI_SISC_LBAE           4               /* Slave access error bit */
+#define        FSI_SISC_LBOE           5               /* Slave lcl bus owner err */
+#define        FSI_SISC_OPBPA          20              /* Slave OPB parity error */
+#define        FSI_SISC_OPBPR          21              /* Slave OPB protocol error */
+#define        FSI_SISC_OPBTO          22              /* Slave OPB timeout error */
+#define        FSI_SISC_OPBEA          23              /* Slave OPB ack error */
+#define        FSI_SISC_CM_ERRS        0x000000f0      /* CMP8 sourced errors */
+#define        FSI_SISC_HM_ERRS        0x0000000f      /* HMP8 sourced errors */
+
+/* FSI slave error interrupt */
+static inline int fsi_sisc_iserror(u32 x)
+{
+       return x & (FSI_SSI_ANY_ERROR3 | FSI_SSI_ANY_ERROR);
+}
+
+/*
+ * FSI slave interrupt mask register: interrupt conditions, status and mask
+ */
+#define        FSI_SSI_ENG0            0x80000000      /* FSI slave */
+#define        FSI_SSI_ENG_MBX         0x400           /* FSI IOU Mailbox */
+#define        FSI_SSI_ENG_ANY         0x7fffffff      /* FSI engine 1..31 */
+#define        FSI_SSI_ENG_NOLBUS      (FSI_SSI_ENG0 | FSI_SSI_ENG_MBX)
+                                               /* Engines without local bus */
+/*
+ * FSI slave status register SSTAT
+ */
+#define        FSI_SSTAT_AE            0x80000000      /* Any error bit */
+#define        FSI_SSTAT_IDD           0x40000000      /* CFAM ID dirty at PON lvl) */
+#define        FSI_SSTAT_LSW           0x40000000      /* Left side warm start flag */
+#define        FSI_SSTAT_RSW           0x10000000      /* Rt side warm start flag */
+#define        FSI_SSTAT_MDL           0x08000000      /* Mail delivered left side */
+#define        FSI_SSTAT_MDR           0x04000000      /* Mail delivered right side */
+#define        FSI_SSTAT_MRL           0x02000000      /* Mail received left side */
+#define        FSI_SSTAT_MRR           0x01000000      /* Mail received right side */
+#define        FSI_SSTAT_BDL_SHIFT     20              /* Brief data left side shft */
+#define        FSI_SSTAT_BDL_MASK      0xf             /* Brief data left side mask */
+#define        FSI_SSTAT_BDR_SHIFT     16              /* Brief data rt side shift */
+#define        FSI_SSTAT_BDR_MASK      0xf             /* Brief data rt side mask */
+#define        FSI_SSTAT_LSLBR         0x8000          /* Left side local bus req */
+#define        FSI_SSTAT_RSLBR         0x4000          /* Right side local bus req */
+#define        FSI_SSTAT_TSLBR         0x2000          /* This side local bus req */
+#define        FSI_SSTAT_BLBA          0x1000          /* Block C-side lcl bus acc */
+#define        FSI_SSTAT_LBO_SHIFT     10              /* Local bus owner shift */
+#define        FSI_SSTAT_LBO_MASK      3               /* Local bus owner mask */
+#define        FSI_SSTAT_TSF_SHIFT     8               /* This side A=01 B=10 C=11 */
+#define        FSI_SSTAT_TSF_MASK      3               /* This side flag mask */
+#define        FSI_SSTAT_CAL           0x00000080      /* Clocks active left port */
+#define        FSI_SSTAT_CAR           0x00000040      /* Clocks active right port */
+#define        FSI_SSTAT_APIL          0x00000020      /* Aux port input level */
+#define        FSI_SSTAT_APRL          0x00000010      /* Aux port reference level */
+#define        FSI_SSTAT_CRC_SHIFT     0               /* CRC error counter */
+#define        FSI_SSTAT_CRC_MASK      0xf             /* CRC mask */
+#define        FSI_SSTAT_SIDE_NONE     0               /* Unknown Side */
+#define        FSI_SSTAT_SIDE_A        1               /* A-Side */
+#define        FSI_SSTAT_SIDE_B        2               /* B-Side */
+#define        FSI_SSTAT_SIDE_C        3               /* C-Side */
+
+/* FSI status local bus request */
+static inline int fsi_sstat_tsf(u32 x)
+{
+       return (x >> FSI_SSTAT_TSF_SHIFT) & FSI_SSTAT_TSF_MASK;
+}
+
+/* FSI status get local bus owner */
+static inline int fsi_sstat_lbo(u32 x)
+{
+       return (x >> FSI_SSTAT_LBO_SHIFT) & FSI_SSTAT_LBO_MASK;
+}
+
+/* FSI status get right side briefing data */
+static inline int fsi_sstat_bdr(u32 x)
+{
+       return (x >> FSI_SSTAT_BDR_SHIFT) & FSI_SSTAT_BDR_MASK;
+}
+
+/* FSI status get left side briefing data */
+static inline int fsi_sstat_bdl(u32 x)
+{
+       return (x >> FSI_SSTAT_BDL_SHIFT) & FSI_SSTAT_BDL_MASK;
+}
+
+/* FSI status get CRC counter */
+static inline int fsi_sstat_crc(u32 x)
+{
+       return (x >> FSI_SSTAT_CRC_SHIFT) & FSI_SSTAT_CRC_MASK;
+}
+
+/*
+ * FSI slave local bus access register SLBUS
+ */
+#define        FSI_SLBUS_FLBO          0x80000000      /* Force local bus ownership */
+#define        FSI_SLBUS_RLBA          0x40000000      /* Request local bus access */
+#define        FSI_SLBUS_RLBO_SHIFT    28              /* Release local bus shift */
+#define        FSI_SLBUS_RLBO_MASK     3               /* Release local bus mask */
+#define        FSI_SLBUS_RLBR          0x08000000      /* Reset local bus req */
+#define        FSI_SLBUS_BLBA_SHIFT    16              /* Block local bus acc shift */
+#define        FSI_SLBUS_BLBA_MASK     0xff            /* Block local bus acc mask */
+#define        FSI_SLBUS_BLBA          0xff            /* Block local bus acc */
+#define        FSI_SLBUS_UBLBA         0xec            /* Unblock local bus access */
+#define        FSI_SLBUS_RESERVE_MASK  0xf8ff0000      /* Mask off reserved bits */
+
+/* Release local bus */
+static inline u32 fsi_slbus_rlbo(int side)
+{
+       return (side & FSI_SLBUS_RLBO_MASK) << FSI_SLBUS_RLBO_SHIFT;
+}
+
+/* Block local bus access */
+static inline u32 fsi_slbus_blba(int side)
+{
+       return (side & FSI_SLBUS_BLBA_MASK) << FSI_SLBUS_BLBA_SHIFT;
+}
+
+/* FSI Slave Error Reset Register SRES */
+#define        FSI_SRES_RFS            0x80000000      /* Reset FSI slave */
+#define        FSI_SRES_REFS           0x40000000      /* Reset Errors FSI slave */
+#define        FSI_SRES_RLBE           0x20000000      /* Reset Local bus engs slave */
+#define        FSI_SRES_RESERVE_MASK   0x1fffffff      /* Mask off reserved bits */
+
+int slave_readreg(struct fsimaster *, void *, u32 *, u32);
+int slave_writereg(struct fsimaster *, void *, u32, u32);
+int slave_irqclear(struct fsimaster *, void *, u32, u32);
+int p8_cfam_fixup(struct fsicfam *, int);
+u32 xmp8_srsim_mask(int);
+
+#endif /* DRIVERS_FSISLAVE_H */

drivers/fsi/ldm.c new file +29 -0

new file mode 100644
index 0000000..4a2f90b
@@ -0,0 +1,29 @@
+/*
+ * FSI interface to the LDM
+ *
+ * Copyright 2016 IBM Corp.
+ *
+ * Christopher Bostic <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+#include "fsi.h"
+#include "fsi_private.h"
+
+/*
+ * Register a FSI device with the Linux device model
+ */
+int fsidev_register_nolock(struct fsidevice *fsidev,
+                          struct device_attribute **ap)
+{
+       return 0;
+}
+
+int fsidev_register(struct fsidevice *fsidev, struct device_attribute **ap)
+{
+       return 0;
+}
+EXPORT_SYMBOL(fsidev_register);

drivers/fsi/readwrite.c new file +34 -1

new file mode 100644
index 0000000..33d972c
@@ -0,0 +1,34 @@
+/*
+ * FSI I/O accesses
+ *
+ * Copyright 2016 IBM Corp.
+ *
+ * Christopher Bostic <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+#include "fsi.h"
+#include "fsi_private.h"
+#include "fsimaster.h"
+
+int fsi_readw_int(struct fsimaster *master, u32 pa, u32 *value)
+{
+       return 0;
+}
+
+int fsi_writew_int(struct fsimaster *master, u32 pa, u32 value)
+{
+       return 0;
+}
+
+/*
+ * Send out a BREAK command on a given link - Resets the logic of any slaves
+ * present
+ */
+int fsi_sendbreak(struct fsimaster *master, u32 cfam_base, int linkno)
+{
+       return 0;
+}
--

1.8.2.2