mx6: ddr: Adjust MDREF register settings for MX6UL

PATCH New Fabio Estevam 2 participants 8 messages Aug 29, 2016 Arm (32-bit)

lore

Share & tools

lore

Fabio Estevam

author

2016-08-29 17:56 UTC #0 lore raw

PATCH v2 1/3 mx6: ddr: Adjust MDREF register settings for MX6UL

From: Fabio Estevam <[email protected]>

When running a NXP 4.1 kernel with U-Boot mainline we observe a hang when going into the lowest operational point of cpufreq.

After comparing the SPL DDR initialization against the DCD table from NXP U-Boot, the key difference that causes the hang is the MDREF register setting.

In all the DDR3 MX6UL boards we have the following configuration for MDREF:

DATA 4 0x021B0020 0x00000800

,which means:

REF_SEL = 0 -->Periodic refresh cycle: 64kHz
REFR = 1 ---> Refresh Rate - 2 refreshes

So adjust the MDREF initialization for MX6UL to fix the kernel hang issue.

Reported-by Eric Nelson <[email protected]>

Signed-off-by Fabio Estevam <[email protected]>

---
Changes since v1:
- Newly introduced in this version

 arch/arm/cpu/armv7/mx6/ddr.c | 12 +++++++++---
 1 file changed, 9 insertions(+), 3 deletions(-)

arch/arm/cpu/armv7/mx6/ddr.c +9 -3

index f151eec..56d3e65 100644
@@ -1183,7 +1183,7 @@ void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo *sysinfo,
 	volatile struct mmdc_p_regs *mmdc0;
 	volatile struct mmdc_p_regs *mmdc1;
 	u32 val;
-	u8 tcke, tcksrx, tcksre, txpdll, taofpd, taonpd, trrd;
+	u8 tcke, tcksrx, tcksre, txpdll, taofpd, taonpd, trrd, refr, refsel;
 	u8 todtlon, taxpd, tanpd, tcwl, txp, tfaw, tcl;
 	u8 todt_idle_off = 0x4; /* from DDR3 Script Aid spreadsheet */
 	u16 trcd, trc, tras, twr, tmrd, trtp, trp, twtr, trfc, txs, txpr;

@@ -1472,9 +1472,15 @@ void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo *sysinfo,
 		MMDC1(mpzqhwctrl, val);
 
 	/* Step 12: Configure and activate periodic refresh */
-	mmdc0->mdref = (1 << 14) | /* REF_SEL: Periodic refresh cycle: 32kHz */
-		       (7 << 11);  /* REFR: Refresh Rate - 8 refreshes */
+	if (!is_mx6ul()) {
+		refsel = 1; /* REF_SEL: Periodic refresh cycle: 32kHz */
+		refr = 7;   /* REFR: Refresh Rate - 8 refreshes */
+	} else {
+		refsel = 0; /* REF_SEL: Periodic refresh cycle: 64kHz */
+		refr = 1;   /* REFR: Refresh Rate - 2 refreshes */
+	}
 
+	mmdc0->mdref = (refsel << 14) | (refr << 11);
 	/* Step 13: Deassert config request - init complete */
 	mmdc0->mdscr = 0x00000000;

Signature · 1 line

1.9.1

Fabio Estevam

author

2016-08-29 17:56 UTC #1 lore raw

PATCH v2 2/3 mx6ul_14x14_evk: Adjust SPL DDR3 settings

From: Fabio Estevam <[email protected]>

Adjust DDR3 initialization done in SPL by comparing them against the NXP DCD table.

Signed-off-by Fabio Estevam <[email protected]>

---
Changes since v1:
- Fix more mismatches

 board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c +7 -7

index c213861..b13f0e2 100644
@@ -777,17 +777,17 @@ static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
 	.dram_odt0 = 0x00000030,
 	.dram_odt1 = 0x00000030,
 	.dram_sdba2 = 0x00000000,
-	.dram_sdclk_0 = 0x00000008,
-	.dram_sdqs0 = 0x00000038,
+	.dram_sdclk_0 = 0x00000030,
+	.dram_sdqs0 = 0x00000030,
 	.dram_sdqs1 = 0x00000030,
 	.dram_reset = 0x00000030,
 };
 
 static struct mx6_mmdc_calibration mx6_mmcd_calib = {
-	.p0_mpwldectrl0 = 0x00070007,
-	.p0_mpdgctrl0 = 0x41490145,
-	.p0_mprddlctl = 0x40404546,
-	.p0_mpwrdlctl = 0x4040524D,
+	.p0_mpwldectrl0 = 0x00000000,
+	.p0_mpdgctrl0 = 0x41570155,
+	.p0_mprddlctl = 0x4040474A,
+	.p0_mpwrdlctl = 0x40405550,
 };
 
 struct mx6_ddr_sysinfo ddr_sysinfo = {

@@ -797,7 +797,7 @@ struct mx6_ddr_sysinfo ddr_sysinfo = {
 	.cs1_mirror = 0,
 	.rtt_wr = 2,
 	.rtt_nom = 1,		/* RTT_Nom = RZQ/2 */
-	.walat = 1,		/* Write additional latency */
+	.walat = 0,		/* Write additional latency */
 	.ralat = 5,		/* Read additional latency */
 	.mif3_mode = 3,		/* Command prediction working mode */
 	.bi_on = 1,		/* Bank interleaving enabled */

Signature · 1 line

1.9.1

Fabio Estevam

author

2016-08-29 17:56 UTC #2 lore raw

PATCH v2 3/3 mx6ul_14x14_ev: Enable the CCGR clocks earlier

In reply to Fabio Estevam

From: Fabio Estevam <[email protected]>

To be in the safe side we need to enable the CCGR clocks prior to calling arch_cpu_init().

Inspired by Tim Harvey's commit d783c2744f9 ("imx: ventana: fix boot to SD").

Signed-off-by Fabio Estevam <[email protected]>

---
Changes since v1:
- Newly introduced in this version

 board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c +2 -2

index b13f0e2..fe81042 100644
@@ -842,11 +842,11 @@ static void spl_dram_init(void)
 
 void board_init_f(ulong dummy)
 {
+	ccgr_init();
+
 	/* setup AIPS and disable watchdog */
 	arch_cpu_init();
 
-	ccgr_init();
-
 	/* iomux and setup of i2c */
 	board_early_init_f();

Signature · 1 line

1.9.1

Eric Nelson

2016-08-29 18:22 UTC #3 lore raw

PATCH v2 3/3 mx6ul_14x14_ev: Enable the CCGR clocks earlier

Hi Fabio,

Quoted 24 lines · Fabio Estevam

From: Fabio Estevam <[email protected]>
To be in the safe side we need to enable the CCGR clocks prior to calling arch_cpu_init().
Inspired by Tim Harvey's commit d783c2744f9 ("imx: ventana: fix boot to SD").
Signed-off-by Fabio Estevam <[email protected]>
---
Changes since v1:
- Newly introduced in this version
 board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)
board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c +0 -0
index b13f0e2..fe81042 100644
@@ -842,11 +842,11 @@ static void spl_dram_init(void)
 
 void board_init_f(ulong dummy)
 {

board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c static void spl_dram_init(void) · line 852

Quoted 10 lines

board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c +2 -2

+	ccgr_init();
+
 	/* setup AIPS and disable watchdog */
 	arch_cpu_init();
 
-	ccgr_init();
-
 	/* iomux and setup of i2c */
 	board_early_init_f();

Reviewed-by Eric Nelson <[email protected]>

Tested-by Eric Nelson <[email protected]>

Eric Nelson

2016-08-29 18:48 UTC #4 lore raw

PATCH v2 1/3 mx6: ddr: Adjust MDREF register settings for MX6UL

In reply to Fabio Estevam

Hi Fabio,

Quoted 5 lines · Fabio Estevam

From: Fabio Estevam <[email protected]>
When running a NXP 4.1 kernel with U-Boot mainline we observe a hang when going into the lowest operational point of cpufreq.

Quoted 7 lines

After comparing the SPL DDR initialization against the DCD table from NXP U-Boot, the key difference that causes the hang is the MDREF register setting.
In all the DDR3 MX6UL boards we have the following configuration for MDREF:

I think this commit message needs work.

"we have" seems to mean that the NXP U-Boot fork has this setting, but this isn't an explanation of why.

Quoted 33 lines

DATA 4 0x021B0020 0x00000800
,which means:
REF_SEL = 0 -->Periodic refresh cycle: 64kHz
REFR = 1 ---> Refresh Rate - 2 refreshes
So adjust the MDREF initialization for MX6UL to fix the kernel hang issue.
Reported-by Eric Nelson <[email protected]>
Signed-off-by Fabio Estevam <[email protected]>
---
Changes since v1:
- Newly introduced in this version
 arch/arm/cpu/armv7/mx6/ddr.c | 12 +++++++++---
 1 file changed, 9 insertions(+), 3 deletions(-)
arch/arm/cpu/armv7/mx6/ddr.c +1 -1
index f151eec..56d3e65 100644
@@ -1183,7 +1183,7 @@ void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo *sysinfo,
 	volatile struct mmdc_p_regs *mmdc0;
 	volatile struct mmdc_p_regs *mmdc1;
 	u32 val;
-	u8 tcke, tcksrx, tcksre, txpdll, taofpd, taonpd, trrd;
+	u8 tcke, tcksrx, tcksre, txpdll, taofpd, taonpd, trrd, refr, refsel;
 	u8 todtlon, taxpd, tanpd, tcwl, txp, tfaw, tcl;
 	u8 todt_idle_off = 0x4; /* from DDR3 Script Aid spreadsheet */
 	u16 trcd, trc, tras, twr, tmrd, trtp, trp, twtr, trfc, txs, txpr;

arch/arm/cpu/armv7/mx6/ddr.c void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo *sysinfo, · line 1476

Quoted 5 lines

arch/arm/cpu/armv7/mx6/ddr.c +0 -2

@@ -1472,9 +1472,15 @@ void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo *sysinfo,
 		MMDC1(mpzqhwctrl, val);
 
 	/* Step 12: Configure and activate periodic refresh */
-	mmdc0->mdref = (1 << 14) | /* REF_SEL: Periodic refresh cycle: 32kHz */
-		       (7 << 11);  /* REFR: Refresh Rate - 8 refreshes */

I'm not understanding why this is CPU specific. Is the issue

arch/arm/cpu/armv7/mx6/ddr.c void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo *sysinfo, · line 1475

Quoted 1 line

arch/arm/cpu/armv7/mx6/ddr.c +1 -0
+	if (!is_mx6ul()) {

Table 44-15 of the 6DQ reference manual says that this will generate tREFI at 3.9uS (256kHz).

arch/arm/cpu/armv7/mx6/ddr.c void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo *sysinfo, · line 1478

Quoted 3 lines

arch/arm/cpu/armv7/mx6/ddr.c +3 -0

+		refsel = 1; /* REF_SEL: Periodic refresh cycle: 32kHz */
+		refr = 7;   /* REFR: Refresh Rate - 8 refreshes */
+	} else {

Table 33-15 of the 6UL manual says 7.8us (128 kHz).

arch/arm/cpu/armv7/mx6/ddr.c void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo *sysinfo, · line 1486

Quoted 9 lines

arch/arm/cpu/armv7/mx6/ddr.c +4 -0

+		refsel = 0; /* REF_SEL: Periodic refresh cycle: 64kHz */
+		refr = 1;   /* REFR: Refresh Rate - 2 refreshes */
+	}
 
+	mmdc0->mdref = (refsel << 14) | (refr << 11);
 	/* Step 13: Deassert config request - init complete */
 	mmdc0->mdscr = 0x00000000;

I did test this patch though, and I can confirm that the problem I experienced (hang with low bus frequency) goes away with just this change, so

Tested-by Eric Nelson <[email protected]>

Eric Nelson

2016-08-29 19:17 UTC #5 lore raw

PATCH v2 1/3 mx6: ddr: Adjust MDREF register settings for MX6UL

Hi Fabio,

Quoted 12 lines · Eric Nelson

Hi Fabio,
Quoted 9 lines · Fabio Estevam
From: Fabio Estevam <[email protected]>
When running a NXP 4.1 kernel with U-Boot mainline we observe a hang when going into the lowest operational point of cpufreq.
After comparing the SPL DDR initialization against the DCD table from NXP U-Boot, the key difference that causes the hang is the MDREF register setting.

Quoted 9 lines

Quoted 3 lines
In all the DDR3 MX6UL boards we have the following configuration for MDREF:
I think this commit message needs work.
"we have" seems to mean that the NXP U-Boot fork has this setting, but this isn't an explanation of why.

After reviewing the manual, I think I understand why this is needed and something like this is probably better:

The i.MX6UL kernel uses a 32kHz clock for to drive refresh in low power mode. Configure the MMDC to use it as the input for refresh in MMDC_MDREF.

Quoted 41 lines

Quoted 33 lines
DATA 4 0x021B0020 0x00000800
,which means:
REF_SEL = 0 -->Periodic refresh cycle: 64kHz
REFR = 1 ---> Refresh Rate - 2 refreshes
So adjust the MDREF initialization for MX6UL to fix the kernel hang issue.
Reported-by Eric Nelson <[email protected]>
Signed-off-by Fabio Estevam <[email protected]>
---
Changes since v1:
- Newly introduced in this version
 arch/arm/cpu/armv7/mx6/ddr.c | 12 +++++++++---
 1 file changed, 9 insertions(+), 3 deletions(-)
arch/arm/cpu/armv7/mx6/ddr.c +1 -1
index f151eec..56d3e65 100644
@@ -1183,7 +1183,7 @@ void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo *sysinfo,
 	volatile struct mmdc_p_regs *mmdc0;
 	volatile struct mmdc_p_regs *mmdc1;
 	u32 val;
-	u8 tcke, tcksrx, tcksre, txpdll, taofpd, taonpd, trrd;
+	u8 tcke, tcksrx, tcksre, txpdll, taofpd, taonpd, trrd, refr, refsel;
 	u8 todtlon, taxpd, tanpd, tcwl, txp, tfaw, tcl;
 	u8 todt_idle_off = 0x4; /* from DDR3 Script Aid spreadsheet */
 	u16 trcd, trc, tras, twr, tmrd, trtp, trp, twtr, trfc, txs, txpr;
arch/arm/cpu/armv7/mx6/ddr.c void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo *sysinfo, · line 1476
Quoted 5 lines
arch/arm/cpu/armv7/mx6/ddr.c +0 -2
@@ -1472,9 +1472,15 @@ void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo *sysinfo,
 		MMDC1(mpzqhwctrl, val);
 
 	/* Step 12: Configure and activate periodic refresh */
-	mmdc0->mdref = (1 << 14) | /* REF_SEL: Periodic refresh cycle: 32kHz */
-		       (7 << 11);  /* REFR: Refresh Rate - 8 refreshes */
I'm not understanding why this is CPU specific. Is the issue

Quoted 5 lines

arch/arm/cpu/armv7/mx6/ddr.c void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo *sysinfo, · line 1475
Quoted 1 line
arch/arm/cpu/armv7/mx6/ddr.c +1 -0
+	if (!is_mx6ul()) {
Table 44-15 of the 6DQ reference manual says that this will generate tREFI at 3.9uS (256kHz).

Never mind. Your comment is about the input clock, not the refresh cycle.

I do wonder if both of these settings don't over-refresh the DDR3 though.

Quoted 22 lines

arch/arm/cpu/armv7/mx6/ddr.c void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo *sysinfo, · line 1478
Quoted 3 lines
arch/arm/cpu/armv7/mx6/ddr.c +3 -0
+		refsel = 1; /* REF_SEL: Periodic refresh cycle: 32kHz */
+		refr = 7;   /* REFR: Refresh Rate - 8 refreshes */
+	} else {
Table 33-15 of the 6UL manual says 7.8us (128 kHz).
arch/arm/cpu/armv7/mx6/ddr.c void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo *sysinfo, · line 1486
Quoted 9 lines
arch/arm/cpu/armv7/mx6/ddr.c +4 -0
+		refsel = 0; /* REF_SEL: Periodic refresh cycle: 64kHz */
+		refr = 1;   /* REFR: Refresh Rate - 2 refreshes */
+	}
 
+	mmdc0->mdref = (refsel << 14) | (refr << 11);
 	/* Step 13: Deassert config request - init complete */
 	mmdc0->mdscr = 0x00000000;
 
I did test this patch though, and I can confirm that the problem I experienced (hang with low bus frequency) goes away with just this change, so
Tested-by Eric Nelson <[email protected]>

Fabio Estevam

author

2016-08-29 19:53 UTC #6 lore raw

PATCH v2 1/3 mx6: ddr: Adjust MDREF register settings for MX6UL

In reply to Eric Nelson

Hi Eric,

Quoted 4 lines · Eric Nelson

I think this commit message needs work.
"we have" seems to mean that the NXP U-Boot fork has this setting, but this isn't an explanation of why.

Would you prefer something like this in ddr.c?
http://pastebin.com/GYBTSFkM

and then on the board file:

http://pastebin.com/cEqvUJwg

Eric Nelson

2016-08-29 20:40 UTC #7 lore raw

PATCH v2 1/3 mx6: ddr: Adjust MDREF register settings for MX6UL

Hi Fabio,

Quoted 9 lines · Fabio Estevam

Hi Eric,
Quoted 4 lines · Eric Nelson
I think this commit message needs work.
"we have" seems to mean that the NXP U-Boot fork has this setting, but this isn't an explanation of why.

Quoted 7 lines

Would you prefer something like this in ddr.c?
http://pastebin.com/GYBTSFkM
and then on the board file:
http://pastebin.com/cEqvUJwg

I'm actually not sure because I haven't quite figured out where the 32k and 64k clock roots are being passed into the MMDC.

If these are configured in a way that allow the kernel implementations to disable one of them, then this should be a board-specific setting to allow different choices.

Or is the inability to use the 64k clock driven by the i.MX6UL somehow? If that's the case, then your original patch is more correct.

I'm also not sure why the NXP U-Boot is decreasing the refresh rate on the 6UL EVK.

Regards,

Eric