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Patch "clk: renesas: r8a7795: Fix SD clocks" has been added to the 4.7-stable tree

PATCH [email protected] 1 participant 1 message Sep 2, 2016

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Stable branch Common clk Renesas clock drivers
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This is a note to let you know that I've just added the patch titled

clk: renesas: r8a7795: Fix SD clocks

to the 4.7-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:

     clk-renesas-r8a7795-fix-sd-clocks.patch

and it can be found in the queue-4.7 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree, please let <[email protected]> know about it.

Quoted 1 line

From e0cb1b84163720ec67ff0e54397fd3f57ad4a4dd Mon Sep 17 00:00:00 2001

From: Yoshihiro Shimoda <[email protected]>
Date: Wed, 10 Aug 2016 09:29:43 +0200
Subject: clk: renesas: r8a7795: Fix SD clocks

From: Yoshihiro Shimoda <[email protected]>

commit e0cb1b84163720ec67ff0e54397fd3f57ad4a4dd upstream.

According to the datasheet, SDn clocks are from the SDSRC clock. And the SDSRC has a 1/2 divider. So, we should have ".sdsrc" as an internal core clock. Otherwise, since the sdhi driver will calculate clock for a sd card using the wrong parent clock rate, and then performance will be not good.

Fixes 90c073e53909da85 ("clk: shmobile: r8a7795: Add SD divider support")
Signed-off-by Yoshihiro Shimoda <[email protected]>
Acked-by Dirk Behme <[email protected]>
Tested-by Wolfram Sang <[email protected]>
Signed-off-by Geert Uytterhoeven <[email protected]>
Signed-off-by Stephen Boyd <[email protected]>
Signed-off-by Greg Kroah-Hartman <[email protected]>
---
 drivers/clk/renesas/r8a7795-cpg-mssr.c |    9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)
drivers/clk/renesas/r8a7795-cpg-mssr.c +5 -4
@@ -91,6 +91,7 @@ static const struct cpg_core_clk r8a7795
 	DEF_FIXED(".s1",        CLK_S1,            CLK_PLL1_DIV2,  3, 1),
 	DEF_FIXED(".s2",        CLK_S2,            CLK_PLL1_DIV2,  4, 1),
 	DEF_FIXED(".s3",        CLK_S3,            CLK_PLL1_DIV2,  6, 1),
+	DEF_FIXED(".sdsrc",     CLK_SDSRC,         CLK_PLL1_DIV2,  2, 1),
 
 	/* Core Clock Outputs */
 	DEF_FIXED("ztr",        R8A7795_CLK_ZTR,   CLK_PLL1_DIV2,  6, 1),

@@ -109,10 +110,10 @@ static const struct cpg_core_clk r8a7795
 	DEF_FIXED("s3d2",       R8A7795_CLK_S3D2,  CLK_S3,         2, 1),
 	DEF_FIXED("s3d4",       R8A7795_CLK_S3D4,  CLK_S3,         4, 1),
 
-	DEF_GEN3_SD("sd0",      R8A7795_CLK_SD0,   CLK_PLL1_DIV2, 0x0074),
-	DEF_GEN3_SD("sd1",      R8A7795_CLK_SD1,   CLK_PLL1_DIV2, 0x0078),
-	DEF_GEN3_SD("sd2",      R8A7795_CLK_SD2,   CLK_PLL1_DIV2, 0x0268),
-	DEF_GEN3_SD("sd3",      R8A7795_CLK_SD3,   CLK_PLL1_DIV2, 0x026c),
+	DEF_GEN3_SD("sd0",      R8A7795_CLK_SD0,   CLK_SDSRC,     0x0074),
+	DEF_GEN3_SD("sd1",      R8A7795_CLK_SD1,   CLK_SDSRC,     0x0078),
+	DEF_GEN3_SD("sd2",      R8A7795_CLK_SD2,   CLK_SDSRC,     0x0268),
+	DEF_GEN3_SD("sd3",      R8A7795_CLK_SD3,   CLK_SDSRC,     0x026c),
 
 	DEF_FIXED("cl",         R8A7795_CLK_CL,    CLK_PLL1_DIV2, 48, 1),
 	DEF_FIXED("cp",         R8A7795_CLK_CP,    CLK_EXTAL,      2, 1),

Patches currently in stable-queue which might be from [email protected] are

queue-4.7/usb-renesas_usbhs-fix-receiving-data-corrupt-on-r-car-gen3-with-dmac.patch queue-4.7/usb-renesas_usbhs-clear-the-brdysts-in-usbhsg_ep_enable.patch queue-4.7/usb-renesas_usbhs-use-dmac-only-if-the-pipe-type-is-bulk.patch queue-4.7/clk-renesas-r8a7795-fix-sd-clocks.patch