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FAILED: patch "[PATCH] drm/i915/gen6+: Interpret mailbox error flags" failed to apply to 4.7-stable tree

PATCH [email protected] 1 participant 1 message Sep 9, 2016

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The patch below does not apply to the 4.7-stable tree.
If someone wants it applied there, or to any other stable or longterm tree, then please email the backport, including the original git commit id to <[email protected]>.

thanks,

greg k-h

------------------ original commit in Linus's tree ------------------

Quoted 1 line

From 5bc6abe7674d9cf41dbcdaaf98a19184da181439 Mon Sep 17 00:00:00 2001

From: Lyude <[email protected]>
Date: Wed, 17 Aug 2016 15:55:53 -0400
Subject: [PATCH] drm/i915/gen6+: Interpret mailbox error flags
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

In order to add proper support for the SAGV, we need to be able to know what the cause of a failure to change the SAGV through the pcode mailbox was. The reasoning for this is that some very early pre-release Skylake machines don't actually allow you to control the SAGV on them, and indicate an invalid mailbox command was sent.

This also might come in handy in the future for debugging.

Changes since v1:
- Add functions for interpreting gen6 mailbox error codes along with gen7+ error codes, and actually interpret those codes properly
- Renamed patch to reflect new behavior

Cc Matt Roper <[email protected]>
Cc Maarten Lankhorst <[email protected]>
Cc Daniel Vetter <[email protected]>
Cc Ville Syrjälä <[email protected]>
[mlankhorst: -ENOSYS -> -ENXIO for checkpatch]
(cherry picked from commit 87660502f1a4d51fb043e89a45d30c9917787c22)
drivers/gpu/drm/i915/i915_reg.h +9 -0
index 5c06413ae0e6..2b9508dda759 100644
@@ -7145,6 +7145,15 @@ enum {
 
 #define GEN6_PCODE_MAILBOX			_MMIO(0x138124)
 #define   GEN6_PCODE_READY			(1<<31)
+#define   GEN6_PCODE_ERROR_MASK			0xFF
+#define     GEN6_PCODE_SUCCESS			0x0
+#define     GEN6_PCODE_ILLEGAL_CMD		0x1
+#define     GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x2
+#define     GEN6_PCODE_TIMEOUT			0x3
+#define     GEN6_PCODE_UNIMPLEMENTED_CMD	0xFF
+#define     GEN7_PCODE_TIMEOUT			0x2
+#define     GEN7_PCODE_ILLEGAL_DATA		0x3
+#define     GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x10
 #define	  GEN6_PCODE_WRITE_RC6VIDS		0x4
 #define	  GEN6_PCODE_READ_RC6VIDS		0x5
 #define     GEN6_ENCODE_RC6_VID(mv)		(((mv) - 245) / 5)
drivers/gpu/drm/i915/intel_pm.c +70 -1

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