Patch "ARM: imx6: add missing BM_CLPCR_BYPASS_PMIC_READY setting for imx6sx" has been added to the 4.7-stable tree

This is a note to let you know that I've just added the patch titled

ARM: imx6: add missing BM_CLPCR_BYPASS_PMIC_READY setting for imx6sx

to the 4.7-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
arm-imx6-add-missing-bm_clpcr_bypass_pmic_ready-setting-for-imx6sx.patch
and it can be found in the queue-4.7 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree, please let <[email protected]> know about it.

From: Anson Huang <[email protected]>
Date: Mon, 22 Aug 2016 23:53:25 +0800
Subject: ARM: imx6: add missing BM_CLPCR_BYPASS_PMIC_READY setting for imx6sx

From: Anson Huang <[email protected]>

commit 8aade778f787305fdbfd3c1d54e6b583601b5902 upstream.

i.MX6SX has bypass PMIC ready function, as this function is normally NOT enabled on the board design, so we need to bypass the PMIC ready pin check during DSM mode resume flow, otherwise, the internal DSM resume logic will be waiting for this signal to be ready forever and cause resume fail.

---
 arch/arm/mach-imx/pm-imx6.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

@@ -310,7 +310,7 @@ int imx6_set_lpm(enum mxc_cpu_pwr_mode m
 		val |= 0x3 << BP_CLPCR_STBY_COUNT;
 		val |= BM_CLPCR_VSTBY;
 		val |= BM_CLPCR_SBYOS;
-		if (cpu_is_imx6sl())
+		if (cpu_is_imx6sl() || cpu_is_imx6sx())
 			val |= BM_CLPCR_BYPASS_PMIC_READY;
 		if (cpu_is_imx6sl() || cpu_is_imx6sx() || cpu_is_imx6ul())
 			val |= BM_CLPCR_BYP_MMDC_CH0_LPM_HS;

Patches currently in stable-queue which might be from [email protected] are

queue-4.7/arm-imx6-add-missing-bm_clpcr_bypass_pmic_ready-setting-for-imx6sx.patch