Patch "perf/x86/intel: Fix PEBSv3 record drain" has been added to the 4.7-stable tree

This is a note to let you know that I've just added the patch titled

perf/x86/intel: Fix PEBSv3 record drain

to the 4.7-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
perf-x86-intel-fix-pebsv3-record-drain.patch
and it can be found in the queue-4.7 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree, please let <[email protected]> know about it.

From: Peter Zijlstra <[email protected]>
Date: Wed, 7 Sep 2016 14:42:55 +0200
Subject: perf/x86/intel: Fix PEBSv3 record drain

From: Peter Zijlstra <[email protected]>

commit 8ef9b8455a2a3049efa9e46e8a6402b972a3eb41 upstream.

Alexander hit the WARN_ON_ONCE(!event) on his Skylake while running the perf fuzzer.

This means the PEBSv3 record included a status bit for an inactive event, something that _should_ not happen.

Move the code that filters the status bits against our known PEBS events up a spot to guarantee we only deal with events we know about.

Further add "continue" statements to the WARN_ON_ONCE()s such that we'll not die nor generate silly events in case we ever do hit them again.

---
 arch/x86/events/intel/ds.c |   19 +++++++++++--------
 1 file changed, 11 insertions(+), 8 deletions(-)

@@ -1274,18 +1274,18 @@ static void intel_pmu_drain_pebs_nhm(str
 		struct pebs_record_nhm *p = at;
 		u64 pebs_status;
 
-		/* PEBS v3 has accurate status bits */
+		pebs_status = p->status & cpuc->pebs_enabled;
+		pebs_status &= (1ULL << x86_pmu.max_pebs_events) - 1;
+
+		/* PEBS v3 has more accurate status bits */
 		if (x86_pmu.intel_cap.pebs_format >= 3) {
-			for_each_set_bit(bit, (unsigned long *)&p->status,
-					 MAX_PEBS_EVENTS)
+			for_each_set_bit(bit, (unsigned long *)&pebs_status,
+					 x86_pmu.max_pebs_events)
 				counts[bit]++;
 
 			continue;
 		}
 
-		pebs_status = p->status & cpuc->pebs_enabled;
-		pebs_status &= (1ULL << x86_pmu.max_pebs_events) - 1;
-
 		/*
 		 * On some CPUs the PEBS status can be zero when PEBS is
 		 * racing with clearing of GLOBAL_STATUS.

@@ -1333,8 +1333,11 @@ static void intel_pmu_drain_pebs_nhm(str
 			continue;
 
 		event = cpuc->events[bit];
-		WARN_ON_ONCE(!event);
-		WARN_ON_ONCE(!event->attr.precise_ip);
+		if (WARN_ON_ONCE(!event))
+			continue;
+
+		if (WARN_ON_ONCE(!event->attr.precise_ip))
+			continue;
 
 		/* log dropped samples number */
 		if (error[bit])

Patches currently in stable-queue which might be from [email protected] are

queue-4.7/perf-x86-intel-pt-fix-an-off-by-one-in-address-filter-configuration.patch queue-4.7/perf-x86-intel-fix-pebsv3-record-drain.patch queue-4.7/arm64-spinlocks-implement-smp_mb__before_spinlock-as-smp_mb.patch queue-4.7/perf-x86-intel-pt-do-validate-the-size-of-a-kernel-address-filter.patch queue-4.7/sched-core-fix-a-race-between-try_to_wake_up-and-a-woken-up-task.patch queue-4.7/perf-x86-intel-pt-fix-kernel-address-filter-s-offset-validation.patch queue-4.7/perf-x86-amd-make-hw_cache_references-and-hw_cache_misses-measure-l2.patch