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clk: qcom: Misc gcc/mmcc msm8996 fixes

PATCH Applied Rajendra Nayak 3 participants 12 messages Oct 19, 2016 – Feb 24, 2017

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Rajendra Nayak

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#0 lore raw

cover clk: qcom: Misc gcc/mmcc msm8996 fixes

These are some misc fixes in the gcc and mmcc clock drivers for msm8996

Rajendra Nayak (7):
clk: qcom: Mark a few branch clocks with BRANCH_HALT_DELAY
clk: qcom: Add a custom udelay needed for some branch clocks
clk: qcom: Add custom udelays for clks in msm8996
clk: qcom: Add freq tables for a few rcgs
clk: qcom: Mark a few clocks as BRANCH_VOTED
clk: qcom: Add force enable/disable needed for gfx3d rcg on msm8996
clk: qcom: Add some missing gcc clks for msm8996

 drivers/clk/qcom/clk-branch.c                |   5 +-
 drivers/clk/qcom/clk-branch.h                |   2 +
 drivers/clk/qcom/clk-rcg2.c                  |  31 +++-
 drivers/clk/qcom/gcc-msm8996.c               | 254 ++++++++++++++++++++++++++-
 include/dt-bindings/clock/qcom,gcc-msm8996.h |  12 ++
 5 files changed, 291 insertions(+), 13 deletions(-)
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QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
author
#1 lore raw

PATCH 1/7 clk: qcom: Mark a few branch clocks with BRANCH_HALT_DELAY

We seem to have a few branch clocks within gcc for msm8996 which do have a valid halt bit but can't be used to check branch enable/disable status as they rely on external clocks in some cases and in some others only toggle during an ongoing bus transaction.
Mark these with BRANCH_HALT_DELAY, so we just add a delay instead.

Signed-off-by Rajendra Nayak <[email protected]>
---
 drivers/clk/qcom/gcc-msm8996.c | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)
drivers/clk/qcom/gcc-msm8996.c +7 -7
index fe03e6f..4e78924 100644
@@ -1388,7 +1388,7 @@ enum {
 };
 
 static struct clk_branch gcc_usb3_phy_pipe_clk = {
-	.halt_reg = 0x50004,
+	.halt_check = BRANCH_HALT_DELAY,
 	.clkr = {
 		.enable_reg = 0x50004,
 		.enable_mask = BIT(0),

@@ -2442,7 +2442,7 @@ enum {
 };
 
 static struct clk_branch gcc_pcie_0_pipe_clk = {
-	.halt_reg = 0x6b018,
+	.halt_check = BRANCH_HALT_DELAY,
 	.clkr = {
 		.enable_reg = 0x6b018,
 		.enable_mask = BIT(0),

@@ -2517,7 +2517,7 @@ enum {
 };
 
 static struct clk_branch gcc_pcie_1_pipe_clk = {
-	.halt_reg = 0x6d018,
+	.halt_check = BRANCH_HALT_DELAY,
 	.clkr = {
 		.enable_reg = 0x6d018,
 		.enable_mask = BIT(0),

@@ -2592,7 +2592,7 @@ enum {
 };
 
 static struct clk_branch gcc_pcie_2_pipe_clk = {
-	.halt_reg = 0x6e018,
+	.halt_check = BRANCH_HALT_DELAY,
 	.clkr = {
 		.enable_reg = 0x6e018,
 		.enable_mask = BIT(0),

@@ -2721,7 +2721,7 @@ enum {
 };
 
 static struct clk_branch gcc_ufs_tx_symbol_0_clk = {
-	.halt_reg = 0x75018,
+	.halt_check = BRANCH_HALT_DELAY,
 	.clkr = {
 		.enable_reg = 0x75018,
 		.enable_mask = BIT(0),

@@ -2736,7 +2736,7 @@ enum {
 };
 
 static struct clk_branch gcc_ufs_rx_symbol_0_clk = {
-	.halt_reg = 0x7501c,
+	.halt_check = BRANCH_HALT_DELAY,
 	.clkr = {
 		.enable_reg = 0x7501c,
 		.enable_mask = BIT(0),

@@ -2751,7 +2751,7 @@ enum {
 };
 
 static struct clk_branch gcc_ufs_rx_symbol_1_clk = {
-	.halt_reg = 0x75020,
+	.halt_check = BRANCH_HALT_DELAY,
 	.clkr = {
 		.enable_reg = 0x75020,
 		.enable_mask = BIT(0),
Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
#2 lore raw

Re: [PATCH 1/7] clk: qcom: Mark a few branch clocks with BRANCH_HALT_DELAY

Quoted 8 lines · Rajendra Nayak

We seem to have a few branch clocks within gcc for msm8996 which do have a valid halt bit but can't be used to check branch enable/disable status as they rely on external clocks in some cases and in some others only toggle during an ongoing bus transaction.
Mark these with BRANCH_HALT_DELAY, so we just add a delay instead.

Signed-off-by Rajendra Nayak <[email protected]>

---

Srini tells me that if the pcie pipe clocks are enabled after the phy is powered up things work fine and the halt bit checks work. So I don't think we need this patch. Probably the drivers are enabling all their clocks at probe instead of understanding that the phy is outputting a clock that goes into gcc to be gated and then back out into their controller and/or phy.

Also, note that these clocks have parents that should be populated by the phys, but so far we haven't done that. That should be fixed as well.

Signature · 2 lines
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
author
#3 lore raw

Re: [PATCH 1/7] clk: qcom: Mark a few branch clocks with BRANCH_HALT_DELAY

Quoted 10 lines · Stephen Boyd
Quoted 8 lines · Rajendra Nayak

We seem to have a few branch clocks within gcc for msm8996 which do have a valid halt bit but can't be used to check branch enable/disable status as they rely on external clocks in some cases and in some others only toggle during an ongoing bus transaction.
Mark these with BRANCH_HALT_DELAY, so we just add a delay instead.

Signed-off-by Rajendra Nayak <[email protected]>

---

Quoted 6 lines

Srini tells me that if the pcie pipe clocks are enabled after the phy is powered up things work fine and the halt bit checks work. So I don't think we need this patch. Probably the drivers are enabling all their clocks at probe instead of understanding that the phy is outputting a clock that goes into gcc to be gated and then back out into their controller and/or phy.

Sure, I will take a look to see if the usb and ufs clocks show the same behavior, in which case we won't need this patch.

Quoted 5 lines

Also, note that these clocks have parents that should be populated by the phys, but so far we haven't done that. That should be fixed as well.

Signature · 2 lines
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
hosted by The Linux Foundation
author
#4 lore raw

PATCH 2/7 clk: qcom: Add a custom udelay needed for some branch clocks

In reply to Rajendra Nayak

Some branch clocks marked with a BRANCH_HALT_DELAY might need more than the default 10us delay. Have a way to specify a custom delay in such cases

Signed-off-by Rajendra Nayak <[email protected]>
---
 drivers/clk/qcom/clk-branch.c | 5 ++++-
 drivers/clk/qcom/clk-branch.h | 2 ++
 2 files changed, 6 insertions(+), 1 deletion(-)
drivers/clk/qcom/clk-branch.c +4 -1
index 26f7af31..1c11f12 100644
@@ -82,7 +82,10 @@ static int clk_branch_wait(const struct clk_branch *br, bool enabling,
 		return 0;
 
 	if (br->halt_check == BRANCH_HALT_DELAY || (!enabling && voted)) {
-		udelay(10);
+		if (br->udelay)
+			udelay(br->udelay);
+		else
+			udelay(10);
 	} else if (br->halt_check == BRANCH_HALT_ENABLE ||
 		   br->halt_check == BRANCH_HALT ||
 		   (enabling && voted)) {
drivers/clk/qcom/clk-branch.h +2 -0
index 284df3f..4c56a35 100644
@@ -26,6 +26,7 @@
  * @halt_reg: halt register
  * @halt_bit: ANDed with @halt_reg to test for clock halted
  * @halt_check: type of halt checking to perform
+ * @udelay: custom udelay incase of BRANCH_HALT_DELAY, default is 10us
  * @clkr: handle between common and hardware-specific interfaces
  *
  * Clock which can gate its output.

@@ -43,6 +44,7 @@ struct clk_branch {
 #define BRANCH_HALT_ENABLE_VOTED	(BRANCH_HALT_ENABLE | BRANCH_VOTED)
 #define BRANCH_HALT_DELAY		2 /* No bit to check; just delay */
 
+	u32	udelay;
 	struct clk_regmap clkr;
 };
Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
Acked-by on v1 2/7
#5 lore raw

Re: [PATCH 2/7] clk: qcom: Add a custom udelay needed for some branch clocks

Quoted 5 lines · Rajendra Nayak

Some branch clocks marked with a BRANCH_HALT_DELAY might need more than the default 10us delay. Have a way to specify a custom delay in such cases

Signed-off-by Rajendra Nayak <[email protected]>
Acked-by Bjorn Andersson <[email protected]>

Regards,
Bjorn

Quoted 45 lines
---
 drivers/clk/qcom/clk-branch.c | 5 ++++-
 drivers/clk/qcom/clk-branch.h | 2 ++
 2 files changed, 6 insertions(+), 1 deletion(-)
drivers/clk/qcom/clk-branch.c +4 -1
index 26f7af31..1c11f12 100644
@@ -82,7 +82,10 @@ static int clk_branch_wait(const struct clk_branch *br, bool enabling,
 		return 0;
 
 	if (br->halt_check == BRANCH_HALT_DELAY || (!enabling && voted)) {
-		udelay(10);
+		if (br->udelay)
+			udelay(br->udelay);
+		else
+			udelay(10);
 	} else if (br->halt_check == BRANCH_HALT_ENABLE ||
 		   br->halt_check == BRANCH_HALT ||
 		   (enabling && voted)) {
drivers/clk/qcom/clk-branch.h +2 -0
index 284df3f..4c56a35 100644
@@ -26,6 +26,7 @@
  * @halt_reg: halt register
  * @halt_bit: ANDed with @halt_reg to test for clock halted
  * @halt_check: type of halt checking to perform
+ * @udelay: custom udelay incase of BRANCH_HALT_DELAY, default is 10us
  * @clkr: handle between common and hardware-specific interfaces
  *
  * Clock which can gate its output.

@@ -43,6 +44,7 @@ struct clk_branch {
 #define BRANCH_HALT_ENABLE_VOTED	(BRANCH_HALT_ENABLE | BRANCH_VOTED)
 #define BRANCH_HALT_DELAY		2 /* No bit to check; just delay */
 
+	u32	udelay;
 	struct clk_regmap clkr;
 };
Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
author
#6 lore raw

PATCH 3/7 clk: qcom: Add custom udelays for clks in msm8996

In reply to Rajendra Nayak

Some of the branch clocks in msm8996 which are marked with a BRANCH_HALT_DELAY require a little more than the default 10us delay, so specify some custom delays for such clocks

Signed-off-by Rajendra Nayak <[email protected]>
---
 drivers/clk/qcom/gcc-msm8996.c | 9 +++++++++
 1 file changed, 9 insertions(+)
drivers/clk/qcom/gcc-msm8996.c +9 -0
index 4e78924..3c85e05 100644
@@ -1389,6 +1389,7 @@ enum {
 
 static struct clk_branch gcc_usb3_phy_pipe_clk = {
 	.halt_check = BRANCH_HALT_DELAY,
+	.udelay = 50,
 	.clkr = {
 		.enable_reg = 0x50004,
 		.enable_mask = BIT(0),

@@ -2443,6 +2444,7 @@ enum {
 
 static struct clk_branch gcc_pcie_0_pipe_clk = {
 	.halt_check = BRANCH_HALT_DELAY,
+	.udelay = 500,
 	.clkr = {
 		.enable_reg = 0x6b018,
 		.enable_mask = BIT(0),

@@ -2518,6 +2520,7 @@ enum {
 
 static struct clk_branch gcc_pcie_1_pipe_clk = {
 	.halt_check = BRANCH_HALT_DELAY,
+	.udelay = 500,
 	.clkr = {
 		.enable_reg = 0x6d018,
 		.enable_mask = BIT(0),

@@ -2593,6 +2596,7 @@ enum {
 
 static struct clk_branch gcc_pcie_2_pipe_clk = {
 	.halt_check = BRANCH_HALT_DELAY,
+	.udelay = 500,
 	.clkr = {
 		.enable_reg = 0x6e018,
 		.enable_mask = BIT(0),

@@ -2722,6 +2726,7 @@ enum {
 
 static struct clk_branch gcc_ufs_tx_symbol_0_clk = {
 	.halt_check = BRANCH_HALT_DELAY,
+	.udelay = 500,
 	.clkr = {
 		.enable_reg = 0x75018,
 		.enable_mask = BIT(0),

@@ -2737,6 +2742,7 @@ enum {
 
 static struct clk_branch gcc_ufs_rx_symbol_0_clk = {
 	.halt_check = BRANCH_HALT_DELAY,
+	.udelay = 500,
 	.clkr = {
 		.enable_reg = 0x7501c,
 		.enable_mask = BIT(0),

@@ -2752,6 +2758,7 @@ enum {
 
 static struct clk_branch gcc_ufs_rx_symbol_1_clk = {
 	.halt_check = BRANCH_HALT_DELAY,
+	.udelay = 500,
 	.clkr = {
 		.enable_reg = 0x75020,
 		.enable_mask = BIT(0),

@@ -2809,6 +2816,7 @@ enum {
 
 static struct clk_branch gcc_ufs_sys_clk_core_clk = {
 	.halt_check = BRANCH_HALT_DELAY,
+	.udelay = 500,
 	.clkr = {
 		.enable_reg = 0x76030,
 		.enable_mask = BIT(0),

@@ -2821,6 +2829,7 @@ enum {
 
 static struct clk_branch gcc_ufs_tx_symbol_clk_core_clk = {
 	.halt_check = BRANCH_HALT_DELAY,
+	.udelay = 500,
 	.clkr = {
 		.enable_reg = 0x76034,
 		.enable_mask = BIT(0),
Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
author
#7 lore raw

PATCH 4/7 clk: qcom: Add freq tables for a few rcgs

In reply to Rajendra Nayak

Add frequency tables for a few RCG clocks in msm8996

Signed-off-by Rajendra Nayak <[email protected]>
---
 drivers/clk/qcom/gcc-msm8996.c | 25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)
drivers/clk/qcom/gcc-msm8996.c +25 -0
index 3c85e05..f6124cf 100644
@@ -464,10 +464,18 @@ enum {
 	},
 };
 
+static struct freq_tbl ftbl_sdcc1_ice_core_clk_src[] = {
+	F(19200000, P_XO, 1, 0, 0),
+	F(150000000, P_GPLL0, 4, 0, 0),
+	F(300000000, P_GPLL0, 2, 0, 0),
+	{ }
+};
+
 static struct clk_rcg2 sdcc1_ice_core_clk_src = {
 	.cmd_rcgr = 0x13024,
 	.hid_width = 5,
 	.parent_map = gcc_xo_gpll0_gpll4_gpll0_early_div_map,
+	.freq_tbl = ftbl_sdcc1_ice_core_clk_src,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "sdcc1_ice_core_clk_src",
 		.parent_names = gcc_xo_gpll0_gpll4_gpll0_early_div,

@@ -1230,10 +1238,18 @@ enum {
 	},
 };
 
+static const struct freq_tbl ftbl_ufs_ice_core_clk_src[] = {
+	F(19200000, P_XO, 1, 0, 0),
+	F(150000000, P_GPLL0, 4, 0, 0),
+	F(300000000, P_GPLL0, 2, 0, 0),
+	{ }
+};
+
 static struct clk_rcg2 ufs_ice_core_clk_src = {
 	.cmd_rcgr = 0x76014,
 	.hid_width = 5,
 	.parent_map = gcc_xo_gpll0_map,
+	.freq_tbl = ftbl_ufs_ice_core_clk_src,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "ufs_ice_core_clk_src",
 		.parent_names = gcc_xo_gpll0,

@@ -1242,10 +1258,19 @@ enum {
 	},
 };
 
+static const struct freq_tbl ftbl_qspi_ser_clk_src[] = {
+	F(75000000, P_GPLL0, 8, 0, 0),
+	F(150000000, P_GPLL0, 4, 0, 0),
+	F(256000000, P_GPLL4, 1.5, 0, 0),
+	F(300000000, P_GPLL0, 2, 0, 0),
+	{ }
+};
+
 static struct clk_rcg2 qspi_ser_clk_src = {
 	.cmd_rcgr = 0x8b00c,
 	.hid_width = 5,
 	.parent_map = gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div_map,
+	.freq_tbl = ftbl_qspi_ser_clk_src,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "qspi_ser_clk_src",
 		.parent_names = gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div,
Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
Applied
#8 lore raw

Re: [PATCH 4/7] clk: qcom: Add freq tables for a few rcgs

Quoted 4 lines · Rajendra Nayak

Add frequency tables for a few RCG clocks in msm8996

Signed-off-by Rajendra Nayak <[email protected]>

---

Applied to clk-next

Signature · 2 lines
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
author
#9 lore raw

PATCH 5/7 clk: qcom: Mark a few clocks as BRANCH_VOTED

In reply to Rajendra Nayak

Mark some of the bimc and smmu clocks with BRANCH_VOTED so we just add a delay on disable without waiting on the halt status.

Signed-off-by Rajendra Nayak <[email protected]>
---
 drivers/clk/qcom/gcc-msm8996.c | 3 +++
 1 file changed, 3 insertions(+)
drivers/clk/qcom/gcc-msm8996.c +3 -0
index f6124cf..2c01b62 100644
@@ -1341,6 +1341,7 @@ enum {
 
 static struct clk_branch gcc_mmss_bimc_gfx_clk = {
 	.halt_reg = 0x9010,
+	.halt_check = BRANCH_VOTED,
 	.clkr = {
 		.enable_reg = 0x9010,
 		.enable_mask = BIT(0),

@@ -2897,6 +2898,7 @@ enum {
 
 static struct clk_branch gcc_smmu_aggre0_axi_clk = {
 	.halt_reg = 0x81014,
+	.halt_check = BRANCH_VOTED,
 	.clkr = {
 		.enable_reg = 0x81014,
 		.enable_mask = BIT(0),

@@ -2912,6 +2914,7 @@ enum {
 
 static struct clk_branch gcc_smmu_aggre0_ahb_clk = {
 	.halt_reg = 0x81018,
+	.halt_check = BRANCH_VOTED,
 	.clkr = {
 		.enable_reg = 0x81018,
 		.enable_mask = BIT(0),
Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
author
#10 lore raw

PATCH 6/7 clk: qcom: Add force enable/disable needed for gfx3d rcg on msm8996

In reply to Rajendra Nayak

The gfx3d RCG on msm8996 needs to be force enabled/disabled by toggling the CMD_ROOT_EN bit. Add enable/disable ops to clk_gfx3d_ops

Signed-off-by Rajendra Nayak <[email protected]>
---
 drivers/clk/qcom/clk-rcg2.c | 31 ++++++++++++++++++++++++++-----
 1 file changed, 26 insertions(+), 5 deletions(-)
drivers/clk/qcom/clk-rcg2.c +26 -5
index a071bba..6c79cca 100644
@@ -300,7 +300,7 @@ static int clk_rcg2_set_rate_and_parent(struct clk_hw *hw,
 };
 EXPORT_SYMBOL_GPL(clk_rcg2_ops);
 
-static int clk_rcg2_shared_force_enable(struct clk_hw *hw, unsigned long rate)
+static int clk_rcg2_force_enable(struct clk_hw *hw)
 {
 	struct clk_rcg2 *rcg = to_clk_rcg2(hw);
 	const char *name = clk_hw_get_name(hw);

@@ -316,20 +316,39 @@ static int clk_rcg2_shared_force_enable(struct clk_hw *hw, unsigned long rate)
 	for (count = 500; count > 0; count--) {
 		ret = clk_rcg2_is_enabled(hw);
 		if (ret)
-			break;
+			return 0;
 		udelay(1);
 	}
 	if (!count)
 		pr_err("%s: RCG did not turn on\n", name);
 
+	return -ETIMEDOUT;
+}
+
+static void clk_rcg2_force_disable(struct clk_hw *hw)
+{
+	struct clk_rcg2 *rcg = to_clk_rcg2(hw);
+
+	/* clear force enable RCG */
+	regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG,
+			   CMD_ROOT_EN, 0);
+}
+
+static int clk_rcg2_shared_force_enable(struct clk_hw *hw, unsigned long rate)
+{
+	int ret;
+
+	ret = clk_rcg2_force_enable(hw);
+	if (ret)
+		return ret;
+
 	/* set clock rate */
 	ret = __clk_rcg2_set_rate(hw, rate);
 	if (ret)
 		return ret;
 
-	/* clear force enable RCG */
-	return regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG,
-				 CMD_ROOT_EN, 0);
+	clk_rcg2_force_disable(hw);
+	return 0;
 }
 
 static int clk_rcg2_shared_set_rate(struct clk_hw *hw, unsigned long rate,

@@ -801,6 +820,8 @@ static int clk_gfx3d_set_rate(struct clk_hw *hw, unsigned long rate,
 }
 
 const struct clk_ops clk_gfx3d_ops = {
+	.enable = clk_rcg2_force_enable,
+	.disable = clk_rcg2_force_disable,
 	.is_enabled = clk_rcg2_is_enabled,
 	.get_parent = clk_rcg2_get_parent,
 	.set_parent = clk_rcg2_set_parent,
Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
author
#11 lore raw

PATCH 7/7 clk: qcom: Add some missing gcc clks for msm8996

In reply to Rajendra Nayak

Add a few missing gcc clks for msm8996

Signed-off-by Rajendra Nayak <[email protected]>
---
 drivers/clk/qcom/gcc-msm8996.c               | 203 +++++++++++++++++++++++++++
 include/dt-bindings/clock/qcom,gcc-msm8996.h |  12 ++
 2 files changed, 215 insertions(+)
drivers/clk/qcom/gcc-msm8996.c +203 -0
index 2c01b62..43333e9 100644
@@ -260,6 +260,36 @@ enum {
 	},
 };
 
+static struct clk_branch gcc_mmss_gpll0_div_clk = {
+	.halt_check = BRANCH_HALT_DELAY,
+	.clkr = {
+		.enable_reg = 0x5200c,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			.name = "gcc_mmss_gpll0_div_clk",
+			.parent_names = (const char *[]){ "gpll0" },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_mss_gpll0_div_clk = {
+	.halt_check = BRANCH_HALT_DELAY,
+	.clkr = {
+		.enable_reg = 0x5200c,
+		.enable_mask = BIT(2),
+		.hw.init = &(struct clk_init_data){
+			.name = "gcc_mss_gpll0_div_clk",
+			.parent_names = (const char *[]){ "gpll0" },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops
+		},
+	},
+};
+
 static struct clk_alpha_pll gpll4_early = {
 	.offset = 0x77000,
 	.clkr = {

@@ -2866,6 +2896,36 @@ enum {
 	},
 };
 
+static struct clk_branch hlos1_vote_lpass_core_smmu_clk = {
+	.halt_reg = 0x7d010,
+	.halt_check = BRANCH_VOTED,
+	.clkr = {
+		.enable_reg = 0x7d010,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			.name = "hlos1_vote_lpass_core_smmu_clk",
+			.parent_names = (const char *[]){ "config_noc_clk_src" },
+			.num_parents = 1,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch hlos1_vote_lpass_adsp_smmu_clk = {
+	.halt_reg = 0x7d014,
+	.halt_check = BRANCH_VOTED,
+	.clkr = {
+		.enable_reg = 0x7d014,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			.name = "hlos1_vote_lpass_adsp_smmu_clk",
+			.parent_names = (const char *[]){ "config_noc_clk_src" },
+			.num_parents = 1,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
 static struct clk_branch gcc_aggre0_snoc_axi_clk = {
 	.halt_reg = 0x81008,
 	.clkr = {

@@ -2928,6 +2988,35 @@ enum {
 	},
 };
 
+static struct clk_branch gcc_aggre0_noc_qosgen_extref_clk = {
+	.halt_check = BRANCH_HALT_DELAY,
+	.udelay = 500,
+	.clkr = {
+		.enable_reg = 0x8101c,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			.name = "gcc_aggre0_noc_qosgen_extref_clk",
+			.parent_names = (const char *[]){ "xo" },
+			.num_parents = 1,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_aggre1_pnoc_ahb_clk = {
+	.halt_reg = 0x82014,
+	.clkr = {
+		.enable_reg = 0x82014,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			.name = "gcc_aggre1_pnoc_ahb_clk",
+			.parent_names = (const char *[]){ "periph_noc_clk_src" },
+			.num_parents = 1,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
 static struct clk_branch gcc_aggre2_ufs_axi_clk = {
 	.halt_reg = 0x83014,
 	.clkr = {

@@ -2958,6 +3047,34 @@ enum {
 	},
 };
 
+static struct clk_branch gcc_dcc_ahb_clk = {
+	.halt_reg = 0x84004,
+	.clkr = {
+		.enable_reg = 0x84004,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			.name = "gcc_dcc_ahb_clk",
+			.parent_names = (const char *[]){ "config_noc_clk_src" },
+			.num_parents = 1,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_aggre0_noc_mpu_cfg_ahb_clk = {
+	.halt_reg = 0x85000,
+	.clkr = {
+		.enable_reg = 0x85000,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			.name = "gcc_aggre0_noc_mpu_cfg_ahb_clk",
+			.parent_names = (const char *[]){ "config_noc_clk_src" },
+			.num_parents = 1,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
 static struct clk_branch gcc_qspi_ahb_clk = {
 	.halt_reg = 0x8b004,
 	.clkr = {

@@ -3016,6 +3133,20 @@ enum {
 	},
 };
 
+static struct clk_branch gcc_edp_clkref_clk = {
+	.halt_reg = 0x88004,
+	.clkr = {
+		.enable_reg = 0x88004,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			.name = "gcc_edp_clkref_clk",
+			.parent_names = (const char *[]){ "xo" },
+			.num_parents = 1,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
 static struct clk_branch gcc_ufs_clkref_clk = {
 	.halt_reg = 0x88008,
 	.clkr = {

@@ -3072,6 +3203,62 @@ enum {
 	},
 };
 
+static struct clk_branch gcc_mss_cfg_ahb_clk = {
+	.halt_reg = 0x8a000,
+	.clkr = {
+		.enable_reg = 0x8a000,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			.name = "gcc_mss_cfg_ahb_clk",
+			.parent_names = (const char *[]){ "config_noc_clk_src" },
+			.num_parents = 1,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_mss_mnoc_bimc_axi_clk = {
+	.halt_reg = 0x8a004,
+	.clkr = {
+		.enable_reg = 0x8a004,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			.name = "gcc_mss_mnoc_bimc_axi_clk",
+			.parent_names = (const char *[]){ "system_noc_clk_src" },
+			.num_parents = 1,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_mss_snoc_axi_clk = {
+	.halt_reg = 0x8a024,
+	.clkr = {
+		.enable_reg = 0x8a024,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			.name = "gcc_mss_snoc_axi_clk",
+			.parent_names = (const char *[]){ "system_noc_clk_src" },
+			.num_parents = 1,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_mss_q6_bimc_axi_clk = {
+	.halt_reg = 0x8a028,
+	.clkr = {
+		.enable_reg = 0x8a028,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			.name = "gcc_mss_q6_bimc_axi_clk",
+			.parent_names = (const char *[]){ "system_noc_clk_src" },
+			.num_parents = 1,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
 static struct clk_hw *gcc_msm8996_hws[] = {
 	&xo.hw,
 	&gpll0_early_div.hw,

@@ -3330,6 +3517,7 @@ enum {
 	[GCC_AGGRE0_CNOC_AHB_CLK] = &gcc_aggre0_cnoc_ahb_clk.clkr,
 	[GCC_SMMU_AGGRE0_AXI_CLK] = &gcc_smmu_aggre0_axi_clk.clkr,
 	[GCC_SMMU_AGGRE0_AHB_CLK] = &gcc_smmu_aggre0_ahb_clk.clkr,
+	[GCC_AGGRE1_PNOC_AHB_CLK] = &gcc_aggre1_pnoc_ahb_clk.clkr,
 	[GCC_AGGRE2_UFS_AXI_CLK] = &gcc_aggre2_ufs_axi_clk.clkr,
 	[GCC_AGGRE2_USB3_AXI_CLK] = &gcc_aggre2_usb3_axi_clk.clkr,
 	[GCC_QSPI_AHB_CLK] = &gcc_qspi_ahb_clk.clkr,

@@ -3340,6 +3528,21 @@ enum {
 	[GCC_PCIE_CLKREF_CLK] = &gcc_pcie_clkref_clk.clkr,
 	[GCC_RX2_USB2_CLKREF_CLK] = &gcc_rx2_usb2_clkref_clk.clkr,
 	[GCC_RX1_USB2_CLKREF_CLK] = &gcc_rx1_usb2_clkref_clk.clkr,
+	[GCC_AGGRE0_NOC_QOSGEN_EXTREF_CLK] =
+					&gcc_aggre0_noc_qosgen_extref_clk.clkr,
+	[GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK] =
+					&hlos1_vote_lpass_core_smmu_clk.clkr,
+	[GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK] =
+					&hlos1_vote_lpass_adsp_smmu_clk.clkr,
+	[GCC_EDP_CLKREF_CLK] = &gcc_edp_clkref_clk.clkr,
+	[GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
+	[GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr,
+	[GCC_MSS_SNOC_AXI_CLK] = &gcc_mss_snoc_axi_clk.clkr,
+	[GCC_MSS_MNOC_BIMC_AXI_CLK] = &gcc_mss_mnoc_bimc_axi_clk.clkr,
+	[GCC_DCC_AHB_CLK] = &gcc_dcc_ahb_clk.clkr,
+	[GCC_AGGRE0_NOC_MPU_CFG_AHB_CLK] = &gcc_aggre0_noc_mpu_cfg_ahb_clk.clkr,
+	[GCC_MMSS_GPLL0_DIV_CLK] = &gcc_mmss_gpll0_div_clk.clkr,
+	[GCC_MSS_GPLL0_DIV_CLK] = &gcc_mss_gpll0_div_clk.clkr,
 };
 
 static struct gdsc *gcc_msm8996_gdscs[] = {
include/dt-bindings/clock/qcom,gcc-msm8996.h +12 -0
index 1828723..4673094 100644
@@ -233,6 +233,18 @@
 #define GCC_PCIE_CLKREF_CLK					216
 #define GCC_RX2_USB2_CLKREF_CLK					217
 #define GCC_RX1_USB2_CLKREF_CLK					218
+#define GCC_AGGRE0_NOC_QOSGEN_EXTREF_CLK			219
+#define GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK			220
+#define GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK			221
+#define GCC_EDP_CLKREF_CLK					222
+#define GCC_MSS_CFG_AHB_CLK					223
+#define GCC_MSS_Q6_BIMC_AXI_CLK					224
+#define GCC_MSS_SNOC_AXI_CLK					225
+#define GCC_MSS_MNOC_BIMC_AXI_CLK				226
+#define GCC_DCC_AHB_CLK						227
+#define GCC_AGGRE0_NOC_MPU_CFG_AHB_CLK				228
+#define GCC_MMSS_GPLL0_DIV_CLK					229
+#define GCC_MSS_GPLL0_DIV_CLK					230
 
 #define GCC_SYSTEM_NOC_BCR					0
 #define GCC_CONFIG_NOC_BCR					1
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