Patch "drm/i915/gen9: minimum scanlines for Y tile is not always 4" has been added to the 4.8-stable tree
Subsystems (3)
This is a note to let you know that I've just added the patch titled
drm/i915/gen9: minimum scanlines for Y tile is not always 4
to the 4.8-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
drm-i915-gen9-minimum-scanlines-for-y-tile-is-not-always-4.patch
and it can be found in the queue-4.8 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree, please let <[email protected]> know about it.
Quoted 1 line
From
ccc1057477bc99678896b51adce6b6ee4019dc37Mon Sep 17 00:00:00 2001
From: Paulo Zanoni <[email protected]>
Date: Thu, 22 Sep 2016 18:00:31 -0300
Subject: drm/i915/gen9: minimum scanlines for Y tile is not always 4
From: Paulo Zanoni <[email protected]>
commit ccc1057477bc99678896b51adce6b6ee4019dc37 upstream.
During watermarks calculations, this value is used in 3 different places. Only one of them was not using a hardcoded 4. Move the code up so everybody can benefit from the actual value.
This should only help on situations with Y tiling + 90/270 rotation + 1 or 2 bpp or NV12.
--- drivers/gpu/drm/i915/intel_pm.c | 56 ++++++++++++++++++++++------------------ 1 file changed, 32 insertions(+), 24 deletions(-)
drivers/gpu/drm/i915/intel_pm.c +32 -24
@@ -3476,7 +3476,8 @@ static uint32_t skl_wm_method1(uint32_tstatic uint32_t skl_wm_method2 (uint32_t pixel_rate,uint32_t pipe_htotal,uint32_t horiz_pixels,uint8_t cpp, -uint64_t tiling,uint32_t latency) +uint64_t tiling,uint32_t latency, +uint32_t y_min_scanlines) {uint32_t ret;uint32_t plane_bytes_per_line, plane_blocks_per_line;
@@ -3489,9 +3490,9 @@ static uint32_t skl_wm_method2(uint32_tif (tiling ==I915_FORMAT_MOD_Y_TILED || tiling == I915_FORMAT_MOD_Yf_TILED) { - plane_bytes_per_line *=4 ; + plane_bytes_per_line *= y_min_scanlines; plane_blocks_per_line =DIV_ROUND_UP (plane_bytes_per_line,512 ); - plane_blocks_per_line /=4 ; + plane_blocks_per_line /= y_min_scanlines; }else if (tiling ==DRM_FORMAT_MOD_NONE ) { plane_blocks_per_line =DIV_ROUND_UP (plane_bytes_per_line,512 ) +1 ; }else {
@@ -3548,6 +3549,7 @@ static int skl_compute_plane_wm(const stuint8_t cpp;uint32_t width =0 , height =0 ;uint32_t plane_pixel_rate; +uint32_t y_min_scanlines;if (latency ==0 || !cstate->base.active || !intel_pstate->visible) { *enabled = false;
@@ -3563,38 +3565,44 @@ static int skl_compute_plane_wm(const st cpp =drm_format_plane_cpp (fb->pixel_format,0 ); plane_pixel_rate =skl_adjusted_plane_pixel_rate (cstate, intel_pstate); +if (intel_rotation_90_or_270 (pstate->rotation)) { +int cpp = (fb->pixel_format ==DRM_FORMAT_NV12 ) ? +drm_format_plane_cpp (fb->pixel_format,1 ) : +drm_format_plane_cpp (fb->pixel_format,0 ); + +switch (cpp) { +case 1 : + y_min_scanlines =16 ; +break ; +case 2 : + y_min_scanlines =8 ; +break ; +default : +WARN (1 ,"Unsupported pixel depth for rotation" ); +case 4 : + y_min_scanlines =4 ; +break ; + } + }else { + y_min_scanlines =4 ; + } + method1 =skl_wm_method1 (plane_pixel_rate, cpp, latency); method2 =skl_wm_method2 (plane_pixel_rate, cstate->base.adjusted_mode.crtc_htotal, width, cpp, fb->modifier[0 ], - latency); + latency, + y_min_scanlines); plane_bytes_per_line = width * cpp; plane_blocks_per_line =DIV_ROUND_UP (plane_bytes_per_line,512 );if (fb->modifier[0 ] ==I915_FORMAT_MOD_Y_TILED || fb->modifier[0 ] == I915_FORMAT_MOD_Yf_TILED) { -uint32_t min_scanlines =4 ; -uint32_t y_tile_minimum; -if (intel_rotation_90_or_270 (pstate->rotation)) { -int cpp = (fb->pixel_format ==DRM_FORMAT_NV12 ) ? -drm_format_plane_cpp (fb->pixel_format,1 ) : -drm_format_plane_cpp (fb->pixel_format,0 ); - -switch (cpp) { -case 1 : - min_scanlines =16 ; -break ; -case 2 : - min_scanlines =8 ; -break ; -case 8 : -WARN (1 ,"Unsupported pixel depth for rotation" ); - } - } - y_tile_minimum = plane_blocks_per_line * min_scanlines; +uint32_t y_tile_minimum = plane_blocks_per_line * + y_min_scanlines; selected_result =max (method2, y_tile_minimum); }else {if ((ddb_allocation / plane_blocks_per_line) >=1 )
@@ -3609,7 +3617,7 @@ static int skl_compute_plane_wm(const stif (level >=1 && level <=7 ) {if (fb->modifier[0 ] ==I915_FORMAT_MOD_Y_TILED || fb->modifier[0 ] == I915_FORMAT_MOD_Yf_TILED) - res_lines +=4 ; + res_lines += y_min_scanlines;else res_blocks++; }
Patches currently in stable-queue which might be from [email protected] are
queue-4.8/drm-i915-gen9-fix-the-watermark-res_blocks-value.patch queue-4.8/drm-i915-gen9-only-add-the-planes-actually-affected-by-ddb-changes.patch queue-4.8/drm-i915-gen9-fix-the-wawmmemoryreadlatency-implementation.patch queue-4.8/drm-i915-introduce-intel_has_sagv.patch queue-4.8/drm-i915-gen9-fix-plane_blocks_per_line-on-watermarks-calculations.patch queue-4.8/drm-i915-kbl-kbl-also-needs-to-run-the-sagv-code.patch queue-4.8/drm-i915-gen9-minimum-scanlines-for-y-tile-is-not-always-4.patch queue-4.8/drm-i915-sagv-is-not-skl-only-so-rename-a-few-things.patch