Patch "drm/i915: SAGV is not SKL-only, so rename a few things" has been added to the 4.8-stable tree
Subsystems (3)
This is a note to let you know that I've just added the patch titled
drm/i915: SAGV is not SKL-only, so rename a few things
to the 4.8-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
drm-i915-sagv-is-not-skl-only-so-rename-a-few-things.patch
and it can be found in the queue-4.8 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree, please let <[email protected]> know about it.
Quoted 1 line
From
674f823b455cdb94d5773406c1caac170f87e1c4Mon Sep 17 00:00:00 2001
From: Paulo Zanoni <[email protected]>
Date: Thu, 22 Sep 2016 18:00:27 -0300
Subject: drm/i915: SAGV is not SKL-only, so rename a few things
From: Paulo Zanoni <[email protected]>
commit 674f823b455cdb94d5773406c1caac170f87e1c4 upstream.
The plan is to introduce intel_has_sagv() and then use it to discover which platforms actually support it.
I thought about keeping the functions with their current skl names, but found two problems: (i) skl_has_sagv() would become a very confusing name, and (ii) intel_atomic_commit_tail() doesn't seem to be calling any functions whose name start with a platform name, so the "intel_" naming scheme seems make more sense than the "firstplatorm_" naming scheme here.
--- drivers/gpu/drm/i915/i915_drv.h | 10 +++++----- drivers/gpu/drm/i915/intel_display.c | 8 ++++---- drivers/gpu/drm/i915/intel_drv.h | 6 +++--- drivers/gpu/drm/i915/intel_pm.c | 26 +++++++++++++------------- 4 files changed, 25 insertions(+), 25 deletions(-)
drivers/gpu/drm/i915/i915_drv.h +5 -5
@@ -1967,11 +1967,11 @@ struct drm_i915_private {struct vlv_s0ix_state vlv_s0ix_state;enum { -I915_SKL_SAGV_UNKNOWN =0 , -I915_SKL_SAGV_DISABLED , -I915_SKL_SAGV_ENABLED , -I915_SKL_SAGV_NOT_CONTROLLED - } skl_sagv_status; +I915_SAGV_UNKNOWN =0 , +I915_SAGV_DISABLED , +I915_SAGV_ENABLED , +I915_SAGV_NOT_CONTROLLED + } sagv_status;struct {/*
drivers/gpu/drm/i915/intel_display.c +4 -4
@@ -13891,8 +13891,8 @@ static void intel_atomic_commit_tail(str* SKL workaround: bspec recommends we disable the SAGV when we * have more then one pipe enabled */ -if (IS_SKYLAKE (dev_priv) && !skl_can_enable_sagv (state)) -skl_disable_sagv (dev_priv); +if (IS_SKYLAKE (dev_priv) && !intel_can_enable_sagv (state)) +intel_disable_sagv (dev_priv);intel_modeset_verify_disabled (dev); }
@@ -13950,8 +13950,8 @@ static void intel_atomic_commit_tail(str }if (IS_SKYLAKE (dev_priv) && intel_state->modeset && -skl_can_enable_sagv (state)) -skl_enable_sagv (dev_priv); +intel_can_enable_sagv (state)) +intel_enable_sagv (dev_priv);drm_atomic_helper_commit_hw_done (state);
drivers/gpu/drm/i915/intel_drv.h +3 -3
@@ -1717,9 +1717,9 @@ void ilk_wm_get_hw_state(struct drm_devivoid skl_wm_get_hw_state (struct drm_device *dev);void skl_ddb_get_hw_state (struct drm_i915_private *dev_priv,struct skl_ddb_allocation *ddb/* out */ ); -bool skl_can_enable_sagv (struct drm_atomic_state *state); -int skl_enable_sagv (struct drm_i915_private *dev_priv); -int skl_disable_sagv (struct drm_i915_private *dev_priv); +bool intel_can_enable_sagv (struct drm_atomic_state *state); +int intel_enable_sagv (struct drm_i915_private *dev_priv); +int intel_disable_sagv (struct drm_i915_private *dev_priv);bool skl_ddb_allocation_equals (const struct skl_ddb_allocation *old,const struct skl_ddb_allocation *new,enum pipe pipe);
drivers/gpu/drm/i915/intel_pm.c +13 -13
@@ -2890,12 +2890,12 @@ skl_wm_plane_id(const struct intel_plane* - We're not using an interlaced display configuration */ int -skl_enable_sagv (struct drm_i915_private *dev_priv) +intel_enable_sagv (struct drm_i915_private *dev_priv) {int ret; -if (dev_priv->skl_sagv_status ==I915_SKL_SAGV_NOT_CONTROLLED || - dev_priv->skl_sagv_status ==I915_SKL_SAGV_ENABLED ) +if (dev_priv->sagv_status ==I915_SAGV_NOT_CONTROLLED || + dev_priv->sagv_status ==I915_SAGV_ENABLED )return 0 ;DRM_DEBUG_KMS ("Enabling the SAGV\n" );
@@ -2913,19 +2913,19 @@ skl_enable_sagv(struct drm_i915_private*/ if (ret == -ENXIO ) {DRM_DEBUG_DRIVER ("No SAGV found on system, ignoring\n" ); - dev_priv->skl_sagv_status =I915_SKL_SAGV_NOT_CONTROLLED ; + dev_priv->sagv_status =I915_SAGV_NOT_CONTROLLED ;return 0 ; }else if (ret <0 ) {DRM_ERROR ("Failed to enable the SAGV\n" );return ret; } - dev_priv->skl_sagv_status =I915_SKL_SAGV_ENABLED ; + dev_priv->sagv_status =I915_SAGV_ENABLED ;return 0 ; }static int -skl_do_sagv_disable (struct drm_i915_private *dev_priv) +intel_do_sagv_disable (struct drm_i915_private *dev_priv) {int ret;uint32_t temp =GEN9_SAGV_DISABLE ;
@@ -2939,19 +2939,19 @@ skl_do_sagv_disable(struct drm_i915_priv }int -skl_disable_sagv (struct drm_i915_private *dev_priv) +intel_disable_sagv (struct drm_i915_private *dev_priv) {int ret, result; -if (dev_priv->skl_sagv_status ==I915_SKL_SAGV_NOT_CONTROLLED || - dev_priv->skl_sagv_status ==I915_SKL_SAGV_DISABLED ) +if (dev_priv->sagv_status ==I915_SAGV_NOT_CONTROLLED || + dev_priv->sagv_status ==I915_SAGV_DISABLED )return 0 ;DRM_DEBUG_KMS ("Disabling the SAGV\n" );mutex_lock (&dev_priv->rps.hw_lock);/* bspec says to keep retrying for at least 1 ms */ - ret =wait_for (result =skl_do_sagv_disable (dev_priv),1 ); + ret =wait_for (result =intel_do_sagv_disable (dev_priv),1 );mutex_unlock (&dev_priv->rps.hw_lock);if (ret == -ETIMEDOUT ) {
@@ -2965,18 +2965,18 @@ skl_disable_sagv(struct drm_i915_private*/ if (result == -ENXIO ) {DRM_DEBUG_DRIVER ("No SAGV found on system, ignoring\n" ); - dev_priv->skl_sagv_status =I915_SKL_SAGV_NOT_CONTROLLED ; + dev_priv->sagv_status =I915_SAGV_NOT_CONTROLLED ;return 0 ; }else if (result <0 ) {DRM_ERROR ("Failed to disable the SAGV\n" );return result; } - dev_priv->skl_sagv_status =I915_SKL_SAGV_DISABLED ; + dev_priv->sagv_status =I915_SAGV_DISABLED ;return 0 ; } -bool skl_can_enable_sagv (struct drm_atomic_state *state) +bool intel_can_enable_sagv (struct drm_atomic_state *state) {struct drm_device *dev = state->dev;struct drm_i915_private *dev_priv =to_i915 (dev);
Patches currently in stable-queue which might be from [email protected] are
queue-4.8/drm-i915-gen9-fix-the-watermark-res_blocks-value.patch queue-4.8/drm-i915-gen9-only-add-the-planes-actually-affected-by-ddb-changes.patch queue-4.8/drm-i915-gen9-fix-the-wawmmemoryreadlatency-implementation.patch queue-4.8/drm-i915-introduce-intel_has_sagv.patch queue-4.8/drm-i915-gen9-fix-plane_blocks_per_line-on-watermarks-calculations.patch queue-4.8/drm-i915-kbl-kbl-also-needs-to-run-the-sagv-code.patch queue-4.8/drm-i915-gen9-minimum-scanlines-for-y-tile-is-not-always-4.patch queue-4.8/drm-i915-sagv-is-not-skl-only-so-rename-a-few-things.patch