Skip to contentSkip to conversation

FAILED: patch "[PATCH] drm/i915: Unconditionally flush any chipset buffers before" failed to apply to 4.8-stable tree

PATCH [email protected] 1 participant 1 message Oct 28, 2016

Subsystems (3)
Stable branch DRM drivers Intel i915
lore
Share & tools
lore

[email protected]

author maintainer
#0 lore raw

The patch below does not apply to the 4.8-stable tree.
If someone wants it applied there, or to any other stable or longterm tree, then please email the backport, including the original git commit id to <[email protected]>.

thanks,

greg k-h

------------------ original commit in Linus's tree ------------------

Quoted 1 line

From 600f436801deae65e48404847b61c89b4944e355 Mon Sep 17 00:00:00 2001

From: Chris Wilson <[email protected]>
Date: Thu, 18 Aug 2016 17:16:40 +0100
Subject: [PATCH] drm/i915: Unconditionally flush any chipset buffers before
execbuf
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

If userspace is asynchronously streaming into the batch or other execobjects, we may not flush those writes along with a change in cache domain (as there is no change). Therefore those writes may end up in internal chipset buffers and not visible to the GPU upon execution. We must issue a flush command or otherwise we encounter incoherency in the batchbuffers and the GPU executing invalid commands (i.e. hanging) quite regularly.

v2: Throw a paranoid wmb() into the general flush so that we remain consistent with before.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90841

Fixes 1816f9236303 ("drm/i915: Support creation of unbound wc user...")
Signed-off-by Chris Wilson <[email protected]>
Cc Akash Goel <[email protected]>
Cc Daniel Vetter <[email protected]>
Cc Tvrtko Ursulin <[email protected]>
Tested-by Matti Hämäläinen <[email protected]>
Cc [email protected]
Reviewed-by Mika Kuoppala <[email protected]>
Link http://patchwork.freedesktop.org/patch/msgid/[email protected]
drivers/gpu/drm/i915/i915_drv.h +1 -0
index 35caa9b2f36a..a08d2595cb6d 100644
@@ -3420,6 +3420,7 @@ int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
 /* belongs in i915_gem_gtt.h */
 static inline void i915_gem_chipset_flush(struct drm_i915_private *dev_priv)
 {
+	wmb();
 	if (INTEL_GEN(dev_priv) < 6)
 		intel_gtt_chipset_flush();
 }
drivers/gpu/drm/i915/i915_gem_execbuffer.c +3 -10
index 699315304748..bce587abc601 100644
@@ -1015,8 +1015,6 @@ i915_gem_execbuffer_move_to_gpu(struct drm_i915_gem_request *req,
 {
 	const unsigned int other_rings = eb_other_engines(req);
 	struct i915_vma *vma;
-	uint32_t flush_domains = 0;
-	bool flush_chipset = false;
 	int ret;
 
 	list_for_each_entry(vma, vmas, exec_list) {

@@ -1029,16 +1027,11 @@ i915_gem_execbuffer_move_to_gpu(struct drm_i915_gem_request *req,
 		}
 
 		if (obj->base.write_domain & I915_GEM_DOMAIN_CPU)
-			flush_chipset |= i915_gem_clflush_object(obj, false);
-
-		flush_domains |= obj->base.write_domain;
+			i915_gem_clflush_object(obj, false);
 	}
 
-	if (flush_chipset)
-		i915_gem_chipset_flush(req->engine->i915);
-
-	if (flush_domains & I915_GEM_DOMAIN_GTT)
-		wmb();
+	/* Unconditionally flush any chipset caches (for streaming writes). */
+	i915_gem_chipset_flush(req->engine->i915);
 
 	/* Unconditionally invalidate GPU caches and TLBs. */
 	return req->engine->emit_flush(req, EMIT_INVALIDATE);