Skip to contentSkip to conversation

FAILED: patch "[PATCH] drm/i915: Mark CPU cache as dirty when used for rendering" failed to apply to 4.8-stable tree

PATCH [email protected] 1 participant 1 message Nov 21, 2016

Subsystems (3)
lore
Share & tools
lore

[email protected]

author maintainer
#0 lore raw

The patch below does not apply to the 4.8-stable tree.
If someone wants it applied there, or to any other stable or longterm tree, then please email the backport, including the original git commit id to <[email protected]>.

thanks,

greg k-h

------------------ original commit in Linus's tree ------------------

Quoted 1 line

From 48004881f6935704e5e4ffaf9e0ec921a25db243 Mon Sep 17 00:00:00 2001

From: Chris Wilson <[email protected]>
Date: Mon, 7 Nov 2016 16:52:04 +0000
Subject: [PATCH] drm/i915: Mark CPU cache as dirty when used for rendering
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

On LLC, or even snooped, machines rendering via the GPU ends up in the CPU cache. This cacheline dirt also needs to be flushed to main memory when moving to an incoherent domain, such as the display's scanout engine. Mostly, this happens because either the object is marked as dirty from its first use or is avoided by setting the object into the display domain from the start.

v2: Treat WT as not requiring a clflush prior to use on the display engine as well.

Fixes 0f71979ab7fb ("drm/i915: Performed deferred clflush inside set-cache-level")

References: https://bugs.freedesktop.org/show_bug.cgi?id=95414

Cc Jani Nikula <[email protected]>
Cc Ville Syrjälä <[email protected]>
Cc <[email protected]> # v4.0+
(cherry picked from commit 7aa6ca61ee5546d74b76610894924cdb0d4a1af0)
drivers/gpu/drm/i915/i915_gem_execbuffer.c +8 -0
index 7adb4c77cc7f..a218c2e395e7 100644
@@ -1281,6 +1281,12 @@ i915_gem_validate_context(struct drm_device *dev, struct drm_file *file,
 	return ctx;
 }
 
+static bool gpu_write_needs_clflush(struct drm_i915_gem_object *obj)
+{
+	return !(obj->cache_level == I915_CACHE_NONE ||
+		 obj->cache_level == I915_CACHE_WT);
+}
+
 void i915_vma_move_to_active(struct i915_vma *vma,
 			     struct drm_i915_gem_request *req,
 			     unsigned int flags)
@@ -1311,6 +1317,8 @@ void i915_vma_move_to_active(struct i915_vma *vma,
 
 		/* update for the implicit flush after a batch */
 		obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
+		if (!obj->cache_dirty && gpu_write_needs_clflush(obj))
+			obj->cache_dirty = true;
 	}
 
 	if (flags & EXEC_OBJECT_NEEDS_FENCE)