Patch "perf/x86: Fix full width counter, counter overflow" has been added to the 4.8-stable tree

This is a note to let you know that I've just added the patch titled

perf/x86: Fix full width counter, counter overflow

to the 4.8-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
perf-x86-fix-full-width-counter-counter-overflow.patch
and it can be found in the queue-4.8 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree, please let <[email protected]> know about it.

From: "Peter Zijlstra (Intel)" <[email protected]>
Date: Tue, 29 Nov 2016 20:33:28 +0000
Subject: perf/x86: Fix full width counter, counter overflow

From: Peter Zijlstra (Intel) <[email protected]>

commit 7f612a7f0bc13a2361a152862435b7941156b6af upstream.

Lukasz reported that perf stat counters overflow handling is broken on KNL/SLM.

Both these parts have full_width_write set, and that does indeed have a problem. In order to deal with counter wrap, we must sample the counter at at least half the counter period (see also the sampling theorem) such that we can unambiguously reconstruct the count.

However commit:

069e0c3c4058 ("perf/x86/intel: Support full width counting")

sets the sampling interval to the full period, not half.

Fixing that exposes another issue, in that we must not sign extend the delta value when we shift it right; the counter cannot have decremented after all.

With both these issues fixed, counter overflow functions correctly again.

---
 arch/x86/events/core.c       |    2 +-
 arch/x86/events/intel/core.c |    2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

@@ -68,7 +68,7 @@ u64 x86_perf_event_update(struct perf_ev
 	int shift = 64 - x86_pmu.cntval_bits;
 	u64 prev_raw_count, new_raw_count;
 	int idx = hwc->idx;
-	s64 delta;
+	u64 delta;
 
 	if (idx == INTEL_PMC_IDX_FIXED_BTS)
 		return 0;

@@ -4024,7 +4024,7 @@ __init int intel_pmu_init(void)
 
 	/* Support full width counters using alternative MSR range */
 	if (x86_pmu.intel_cap.full_width_write) {
-		x86_pmu.max_period = x86_pmu.cntval_mask;
+		x86_pmu.max_period = x86_pmu.cntval_mask >> 1;
 		x86_pmu.perfctr = MSR_IA32_PMC0;
 		pr_cont("full-width counters, ");
 	}

Patches currently in stable-queue which might be from [email protected] are

queue-4.8/sched-autogroup-fix-64-bit-kernel-nice-level-adjustment.patch queue-4.8/locking-rtmutex-prevent-dequeue-vs.-unlock-race.patch queue-4.8/perf-x86-fix-full-width-counter-counter-overflow.patch queue-4.8/locking-rtmutex-use-read_once-in-rt_mutex_owner.patch