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Revert "sf: Fix quad bit set for micron devices"

PATCH Superseded Jagan Teki 1 participant 2 messages Dec 15, 2016 – Dec 16, 2016 Memory technology devices (MTD)

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Jagan Teki

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PATCH v2 1/1 Revert "sf: Fix quad bit set for micron devices"

From: Cyrille Pitchen <[email protected]>

This reverts commit c56ae7519f141523ba1248b22b5b5169b21772fe.

Once the 'Quad Enable' bit is cleared in their Enhanced Volatile Configuration Register (EVCR), Micron memories expect ALL commands to use the SPI 4-4-4 protocol. Commands using SPI 1-y-z protocols are no longer accepted.

Within the reverted commit, the write_evcr() function is implemented using the spi_flash_write_common(), which is a shortcut for the
[ spi_flash_cmd_write_enable(), spi_flash_cmd_write(), spi_flash_cmd_wait_ready() ] sequence.

Since the internal state of the Micron memory has been changed when the spi_flash_cmd_write() function completes, the later call of the spi_flash_cmd_wait_ready() function fails.

Indeed the SPI controller driver is not aware of the SPI protocol switch.

Further patches will fix the support of Micron QSPI memories.

[Rebase on master, use JEDEC_MFR(info) in place of idcode0]

---
Changes for v2:
- Rebase and JEDEC_MFR(info) in place of idcode0

 drivers/mtd/spi/sf_internal.h |  3 ---
 drivers/mtd/spi/spi_flash.c   | 62 ++-----------------------------------------
 2 files changed, 2 insertions(+), 63 deletions(-)
drivers/mtd/spi/sf_internal.h +0 -3
index 2463686..839cdbe 100644
@@ -49,7 +49,6 @@ enum spi_nor_option_flags {
 #define CMD_WRITE_DISABLE		0x04
 #define CMD_WRITE_ENABLE		0x06
 #define CMD_QUAD_PAGE_PROGRAM		0x32
-#define CMD_WRITE_EVCR			0x61
 
 /* Read commands */
 #define CMD_READ_ARRAY_SLOW		0x03
@@ -63,7 +62,6 @@ enum spi_nor_option_flags {
 #define CMD_READ_STATUS1		0x35
 #define CMD_READ_CONFIG			0x35
 #define CMD_FLAG_STATUS			0x70
-#define CMD_READ_EVCR			0x65
 
 /* Bank addr access commands */
 #ifdef CONFIG_SPI_FLASH_BAR
@@ -78,7 +76,6 @@ enum spi_nor_option_flags {
 #define STATUS_QEB_WINSPAN		BIT(1)
 #define STATUS_QEB_MXIC			BIT(6)
 #define STATUS_PEC			BIT(7)
-#define STATUS_QEB_MICRON		BIT(7)
 #define SR_BP0				BIT(2)  /* Block protect 0 */
 #define SR_BP1				BIT(3)  /* Block protect 1 */
 #define SR_BP2				BIT(4)  /* Block protect 2 */
drivers/mtd/spi/spi_flash.c +2 -60

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PATCH v2 1/1 Revert "sf: Fix quad bit set for micron devices"

Quoted 18 lines · Jagan Teki

From: Cyrille Pitchen <[email protected]>

This reverts commit c56ae7519f141523ba1248b22b5b5169b21772fe.

Once the 'Quad Enable' bit is cleared in their Enhanced Volatile Configuration Register (EVCR), Micron memories expect ALL commands to use the SPI 4-4-4 protocol. Commands using SPI 1-y-z protocols are no longer accepted.

Within the reverted commit, the write_evcr() function is implemented using the spi_flash_write_common(), which is a shortcut for the
[ spi_flash_cmd_write_enable(), spi_flash_cmd_write(), spi_flash_cmd_wait_ready() ] sequence.

Since the internal state of the Micron memory has been changed when the spi_flash_cmd_write() function completes, the later call of the spi_flash_cmd_wait_ready() function fails.

Quoted 7 lines

Indeed the SPI controller driver is not aware of the SPI protocol switch.

Further patches will fix the support of Micron QSPI memories.

[Rebase on master, use JEDEC_MFR(info) in place of idcode0]

Applied to u-boot-spi/master

thanks!

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Jagan Teki
Free Software Engineer | www.openedev.com
U-Boot, Linux | Upstream Maintainer
Hyderabad, India.