WTF: patch "[PATCH] drm/amdgpu: update tile table for oland/hainan" was seriously submitted to be applied to the 4.9-stable tree?
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maintainerThe patch below was submitted to be applied to the 4.9-stable tree.
I fail to see how this patch meets the stable kernel rules as found at Documentation/stable_kernel_rules.txt.
I could be totally wrong, and if so, please respond to <[email protected]> and let me know why this patch should be applied. Otherwise, it is now dropped from my patch queues, never to be seen again.
thanks,
greg k-h
------------------ original commit in Linus's tree ------------------
Quoted 1 line
From
f8d9422ef80c5126112284493e69c88753c56ad1Mon Sep 17 00:00:00 2001
From: Flora Cui <[email protected]>
Date: Thu, 15 Dec 2016 16:29:31 +0800
Subject: [PATCH] drm/amdgpu: update tile table for oland/hainan
Signed-off-by Flora Cui <[email protected]>
Reviewed-by Junwei Zhang <[email protected]>
Reviewed-by Alex Deucher <[email protected]>
Signed-off-by Alex Deucher <[email protected]>
drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c +191 -139
@@ -708,238 +708,290 @@ static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev)for (reg_offset =0 ; reg_offset < num_tile_mode_states; reg_offset++) {switch (reg_offset) {case 0 : - gb_tile_moden = (ARRAY_MODE (ARRAY_2D_TILED_THIN1 ) | -MICRO_TILE_MODE (ADDR_SURF_DEPTH_MICRO_TILING ) | -PIPE_CONFIG (ADDR_SURF_P4_8x16) | + gb_tile_moden = (MICRO_TILE_MODE (ADDR_SURF_DEPTH_MICRO_TILING ) | +ARRAY_MODE (ARRAY_2D_TILED_THIN1 ) | +PIPE_CONFIG (ADDR_SURF_P2 ) |TILE_SPLIT (ADDR_SURF_TILE_SPLIT_64B ) | -NUM_BANKS (ADDR_SURF_16_BANK ) |BANK_WIDTH (ADDR_SURF_BANK_WIDTH_1 ) |BANK_HEIGHT (ADDR_SURF_BANK_HEIGHT_4 ) | -MACRO_TILE_ASPECT (ADDR_SURF_MACRO_ASPECT_4 )); +MACRO_TILE_ASPECT (ADDR_SURF_MACRO_ASPECT_4 ) | +NUM_BANKS (ADDR_SURF_16_BANK ));break ;case 1 : - gb_tile_moden = (ARRAY_MODE (ARRAY_2D_TILED_THIN1 ) | -MICRO_TILE_MODE (ADDR_SURF_DEPTH_MICRO_TILING ) | -PIPE_CONFIG (ADDR_SURF_P4_8x16) | + gb_tile_moden = (MICRO_TILE_MODE (ADDR_SURF_DEPTH_MICRO_TILING ) | +ARRAY_MODE (ARRAY_2D_TILED_THIN1 ) | +PIPE_CONFIG (ADDR_SURF_P2 ) |TILE_SPLIT (ADDR_SURF_TILE_SPLIT_128B ) | -NUM_BANKS (ADDR_SURF_16_BANK ) |BANK_WIDTH (ADDR_SURF_BANK_WIDTH_1 ) |BANK_HEIGHT (ADDR_SURF_BANK_HEIGHT_4 ) | -MACRO_TILE_ASPECT (ADDR_SURF_MACRO_ASPECT_4 )); +MACRO_TILE_ASPECT (ADDR_SURF_MACRO_ASPECT_4 ) | +NUM_BANKS (ADDR_SURF_16_BANK ));break ;case 2 : - gb_tile_moden = (ARRAY_MODE (ARRAY_2D_TILED_THIN1 ) | -MICRO_TILE_MODE (ADDR_SURF_DEPTH_MICRO_TILING ) | -PIPE_CONFIG (ADDR_SURF_P4_8x16) | + gb_tile_moden = (MICRO_TILE_MODE (ADDR_SURF_DEPTH_MICRO_TILING ) | +ARRAY_MODE (ARRAY_2D_TILED_THIN1 ) | +PIPE_CONFIG (ADDR_SURF_P2 ) |TILE_SPLIT (ADDR_SURF_TILE_SPLIT_256B ) | -NUM_BANKS (ADDR_SURF_16_BANK ) |BANK_WIDTH (ADDR_SURF_BANK_WIDTH_1 ) |BANK_HEIGHT (ADDR_SURF_BANK_HEIGHT_4 ) | -MACRO_TILE_ASPECT (ADDR_SURF_MACRO_ASPECT_4 )); +MACRO_TILE_ASPECT (ADDR_SURF_MACRO_ASPECT_4 ) | +NUM_BANKS (ADDR_SURF_16_BANK ));break ;case 3 : - gb_tile_moden = (ARRAY_MODE (ARRAY_2D_TILED_THIN1 ) | -MICRO_TILE_MODE (ADDR_SURF_DEPTH_MICRO_TILING ) | -PIPE_CONFIG (ADDR_SURF_P4_8x16) | -TILE_SPLIT (ADDR_SURF_TILE_SPLIT_128B ) | -NUM_BANKS (ADDR_SURF_16_BANK ) | + gb_tile_moden = (MICRO_TILE_MODE (ADDR_SURF_DEPTH_MICRO_TILING ) | +ARRAY_MODE (ARRAY_2D_TILED_THIN1 ) | +PIPE_CONFIG (ADDR_SURF_P2 ) |BANK_WIDTH (ADDR_SURF_BANK_WIDTH_1 ) | -BANK_HEIGHT (ADDR_SURF_BANK_HEIGHT_4 ) | -MACRO_TILE_ASPECT (ADDR_SURF_MACRO_ASPECT_4 )); +BANK_HEIGHT (ADDR_SURF_BANK_HEIGHT_2 ) | +MACRO_TILE_ASPECT (ADDR_SURF_MACRO_ASPECT_1 ) | +NUM_BANKS (ADDR_SURF_8_BANK ) | +TILE_SPLIT (split_equal_to_row_size));break ;case 4 : - gb_tile_moden = (ARRAY_MODE (ARRAY_1D_TILED_THIN1 ) | -MICRO_TILE_MODE (ADDR_SURF_DEPTH_MICRO_TILING ) | -PIPE_CONFIG (ADDR_SURF_P4_8x16) | -TILE_SPLIT (ADDR_SURF_TILE_SPLIT_64B ) | -NUM_BANKS (ADDR_SURF_16_BANK ) | -BANK_WIDTH (ADDR_SURF_BANK_WIDTH_1 ) | -BANK_HEIGHT (ADDR_SURF_BANK_HEIGHT_2 ) | -MACRO_TILE_ASPECT (ADDR_SURF_MACRO_ASPECT_2 )); + gb_tile_moden = (MICRO_TILE_MODE (ADDR_SURF_DEPTH_MICRO_TILING ) | +ARRAY_MODE (ARRAY_1D_TILED_THIN1 ) | +PIPE_CONFIG (ADDR_SURF_P2 ));break ;case 5 : - gb_tile_moden = (ARRAY_MODE (ARRAY_2D_TILED_THIN1 ) | -MICRO_TILE_MODE (ADDR_SURF_DEPTH_MICRO_TILING ) | -PIPE_CONFIG (ADDR_SURF_P4_8x16) | -TILE_SPLIT (split_equal_to_row_size) | -NUM_BANKS (ADDR_SURF_16_BANK ) | + gb_tile_moden = (MICRO_TILE_MODE (ADDR_SURF_DEPTH_MICRO_TILING ) | +ARRAY_MODE (ARRAY_2D_TILED_THIN1 ) | +PIPE_CONFIG (ADDR_SURF_P2 ) | +TILE_SPLIT (ADDR_SURF_TILE_SPLIT_512B ) |BANK_WIDTH (ADDR_SURF_BANK_WIDTH_1 ) | -BANK_HEIGHT (ADDR_SURF_BANK_HEIGHT_2 ) | -MACRO_TILE_ASPECT (ADDR_SURF_MACRO_ASPECT_2 )); +BANK_HEIGHT (ADDR_SURF_BANK_HEIGHT_1 ) | +MACRO_TILE_ASPECT (ADDR_SURF_MACRO_ASPECT_1 ) | +NUM_BANKS (ADDR_SURF_8_BANK ));break ;case 6 : - gb_tile_moden = (ARRAY_MODE (ARRAY_2D_TILED_THIN1 ) | -MICRO_TILE_MODE (ADDR_SURF_DEPTH_MICRO_TILING ) | -PIPE_CONFIG (ADDR_SURF_P4_8x16) | -TILE_SPLIT (split_equal_to_row_size) | -NUM_BANKS (ADDR_SURF_16_BANK ) | + gb_tile_moden = (MICRO_TILE_MODE (ADDR_SURF_DEPTH_MICRO_TILING ) | +ARRAY_MODE (ARRAY_2D_TILED_THIN1 ) | +PIPE_CONFIG (ADDR_SURF_P2 ) | +TILE_SPLIT (ADDR_SURF_TILE_SPLIT_256B ) |BANK_WIDTH (ADDR_SURF_BANK_WIDTH_1 ) | -BANK_HEIGHT (ADDR_SURF_BANK_HEIGHT_1 ) | -MACRO_TILE_ASPECT (ADDR_SURF_MACRO_ASPECT_2 )); +BANK_HEIGHT (ADDR_SURF_BANK_HEIGHT_2 ) | +MACRO_TILE_ASPECT (ADDR_SURF_MACRO_ASPECT_1 ) | +NUM_BANKS (ADDR_SURF_8_BANK ));break ;case 7 : - gb_tile_moden = (ARRAY_MODE (ARRAY_2D_TILED_THIN1 ) | -MICRO_TILE_MODE (ADDR_SURF_DEPTH_MICRO_TILING ) | -PIPE_CONFIG (ADDR_SURF_P4_8x16) | -TILE_SPLIT (split_equal_to_row_size) | -NUM_BANKS (ADDR_SURF_16_BANK ) | + gb_tile_moden = (MICRO_TILE_MODE (ADDR_SURF_DEPTH_MICRO_TILING ) | +ARRAY_MODE (ARRAY_2D_TILED_THIN1 ) | +PIPE_CONFIG (ADDR_SURF_P2 ) | +TILE_SPLIT (ADDR_SURF_TILE_SPLIT_1KB ) |BANK_WIDTH (ADDR_SURF_BANK_WIDTH_1 ) | -BANK_HEIGHT (ADDR_SURF_BANK_HEIGHT_4 ) | -MACRO_TILE_ASPECT (ADDR_SURF_MACRO_ASPECT_4 )); +BANK_HEIGHT (ADDR_SURF_BANK_HEIGHT_2 ) | +MACRO_TILE_ASPECT (ADDR_SURF_MACRO_ASPECT_1 ) | +NUM_BANKS (ADDR_SURF_4_BANK ));break ;case 8 : - gb_tile_moden = (ARRAY_MODE (ARRAY_LINEAR_ALIGNED ) | -MICRO_TILE_MODE (ADDR_SURF_DISPLAY_MICRO_TILING ) | -PIPE_CONFIG (ADDR_SURF_P4_8x16) | -TILE_SPLIT (ADDR_SURF_TILE_SPLIT_64B ) | -NUM_BANKS (ADDR_SURF_16_BANK ) | -BANK_WIDTH (ADDR_SURF_BANK_WIDTH_1 ) | -BANK_HEIGHT (ADDR_SURF_BANK_HEIGHT_2 ) | -MACRO_TILE_ASPECT (ADDR_SURF_MACRO_ASPECT_2 )); + gb_tile_moden = (ARRAY_MODE (ARRAY_LINEAR_ALIGNED ));break ;case 9 : - gb_tile_moden = (ARRAY_MODE (ARRAY_1D_TILED_THIN1 ) | -MICRO_TILE_MODE (ADDR_SURF_DISPLAY_MICRO_TILING ) | -PIPE_CONFIG (ADDR_SURF_P4_8x16) | -TILE_SPLIT (ADDR_SURF_TILE_SPLIT_64B ) | -NUM_BANKS (ADDR_SURF_16_BANK ) | -BANK_WIDTH (ADDR_SURF_BANK_WIDTH_1 ) | -BANK_HEIGHT (ADDR_SURF_BANK_HEIGHT_2 ) | -MACRO_TILE_ASPECT (ADDR_SURF_MACRO_ASPECT_2 )); + gb_tile_moden = (MICRO_TILE_MODE (ADDR_SURF_DISPLAY_MICRO_TILING ) | +ARRAY_MODE (ARRAY_1D_TILED_THIN1 ) | +PIPE_CONFIG (ADDR_SURF_P2 ));break ;case 10 : - gb_tile_moden = (ARRAY_MODE (ARRAY_2D_TILED_THIN1 ) | -MICRO_TILE_MODE (ADDR_SURF_DISPLAY_MICRO_TILING ) | -PIPE_CONFIG (ADDR_SURF_P4_8x16) | + gb_tile_moden = (MICRO_TILE_MODE (ADDR_SURF_DISPLAY_MICRO_TILING ) | +ARRAY_MODE (ARRAY_2D_TILED_THIN1 ) | +PIPE_CONFIG (ADDR_SURF_P2 ) |TILE_SPLIT (ADDR_SURF_TILE_SPLIT_256B ) | -NUM_BANKS (ADDR_SURF_16_BANK ) |BANK_WIDTH (ADDR_SURF_BANK_WIDTH_1 ) |BANK_HEIGHT (ADDR_SURF_BANK_HEIGHT_4 ) | -MACRO_TILE_ASPECT (ADDR_SURF_MACRO_ASPECT_4 )); +MACRO_TILE_ASPECT (ADDR_SURF_MACRO_ASPECT_4 ) | +NUM_BANKS (ADDR_SURF_16_BANK ));break ;case 11 : - gb_tile_moden = (ARRAY_MODE (ARRAY_2D_TILED_THIN1 ) | -MICRO_TILE_MODE (ADDR_SURF_DISPLAY_MICRO_TILING ) | -PIPE_CONFIG (ADDR_SURF_P4_8x16) | + gb_tile_moden = (MICRO_TILE_MODE (ADDR_SURF_DISPLAY_MICRO_TILING ) | +ARRAY_MODE (ARRAY_2D_TILED_THIN1 ) | +PIPE_CONFIG (ADDR_SURF_P2 ) |TILE_SPLIT (ADDR_SURF_TILE_SPLIT_256B ) | -NUM_BANKS (ADDR_SURF_16_BANK ) |BANK_WIDTH (ADDR_SURF_BANK_WIDTH_1 ) |BANK_HEIGHT (ADDR_SURF_BANK_HEIGHT_2 ) | -MACRO_TILE_ASPECT (ADDR_SURF_MACRO_ASPECT_2 )); +MACRO_TILE_ASPECT (ADDR_SURF_MACRO_ASPECT_2 ) | +NUM_BANKS (ADDR_SURF_16_BANK ));break ;case 12 : - gb_tile_moden = (ARRAY_MODE (ARRAY_2D_TILED_THIN1 ) | -MICRO_TILE_MODE (ADDR_SURF_DISPLAY_MICRO_TILING ) | -PIPE_CONFIG (ADDR_SURF_P4_8x16) | + gb_tile_moden = (MICRO_TILE_MODE (ADDR_SURF_DISPLAY_MICRO_TILING ) | +ARRAY_MODE (ARRAY_2D_TILED_THIN1 ) | +PIPE_CONFIG (ADDR_SURF_P2 ) |TILE_SPLIT (ADDR_SURF_TILE_SPLIT_512B ) | -NUM_BANKS (ADDR_SURF_16_BANK ) |BANK_WIDTH (ADDR_SURF_BANK_WIDTH_1 ) |BANK_HEIGHT (ADDR_SURF_BANK_HEIGHT_1 ) | -MACRO_TILE_ASPECT (ADDR_SURF_MACRO_ASPECT_2 )); +MACRO_TILE_ASPECT (ADDR_SURF_MACRO_ASPECT_2 ) | +NUM_BANKS (ADDR_SURF_16_BANK ));break ;case 13 : - gb_tile_moden = (ARRAY_MODE (ARRAY_1D_TILED_THIN1 ) | -MICRO_TILE_MODE (ADDR_SURF_THIN_MICRO_TILING ) | -PIPE_CONFIG (ADDR_SURF_P4_8x16) | -TILE_SPLIT (ADDR_SURF_TILE_SPLIT_64B ) | -NUM_BANKS (ADDR_SURF_16_BANK ) | -BANK_WIDTH (ADDR_SURF_BANK_WIDTH_1 ) | -BANK_HEIGHT (ADDR_SURF_BANK_HEIGHT_2 ) | -MACRO_TILE_ASPECT (ADDR_SURF_MACRO_ASPECT_2 )); + gb_tile_moden = (MICRO_TILE_MODE (ADDR_SURF_THIN_MICRO_TILING ) | +ARRAY_MODE (ARRAY_1D_TILED_THIN1 ) | +PIPE_CONFIG (ADDR_SURF_P2 ));break ;case 14 : - gb_tile_moden = (ARRAY_MODE (ARRAY_2D_TILED_THIN1 ) | -MICRO_TILE_MODE (ADDR_SURF_THIN_MICRO_TILING ) | -PIPE_CONFIG (ADDR_SURF_P4_8x16) | + gb_tile_moden = (MICRO_TILE_MODE (ADDR_SURF_THIN_MICRO_TILING ) | +ARRAY_MODE (ARRAY_2D_TILED_THIN1 ) | +PIPE_CONFIG (ADDR_SURF_P2 ) |TILE_SPLIT (ADDR_SURF_TILE_SPLIT_256B ) | -NUM_BANKS (ADDR_SURF_16_BANK ) |BANK_WIDTH (ADDR_SURF_BANK_WIDTH_1 ) |BANK_HEIGHT (ADDR_SURF_BANK_HEIGHT_4 ) | -MACRO_TILE_ASPECT (ADDR_SURF_MACRO_ASPECT_2 )); +MACRO_TILE_ASPECT (ADDR_SURF_MACRO_ASPECT_2 ) | +NUM_BANKS (ADDR_SURF_16_BANK ));break ;case 15 : - gb_tile_moden = (ARRAY_MODE (ARRAY_2D_TILED_THIN1 ) | -MICRO_TILE_MODE (ADDR_SURF_THIN_MICRO_TILING ) | -PIPE_CONFIG (ADDR_SURF_P4_8x16) | + gb_tile_moden = (MICRO_TILE_MODE (ADDR_SURF_THIN_MICRO_TILING ) | +ARRAY_MODE (ARRAY_2D_TILED_THIN1 ) | +PIPE_CONFIG (ADDR_SURF_P2 ) |TILE_SPLIT (ADDR_SURF_TILE_SPLIT_256B ) | -NUM_BANKS (ADDR_SURF_16_BANK ) |BANK_WIDTH (ADDR_SURF_BANK_WIDTH_1 ) |BANK_HEIGHT (ADDR_SURF_BANK_HEIGHT_2 ) | -MACRO_TILE_ASPECT (ADDR_SURF_MACRO_ASPECT_2 )); +MACRO_TILE_ASPECT (ADDR_SURF_MACRO_ASPECT_2 ) | +NUM_BANKS (ADDR_SURF_16_BANK ));break ;case 16 : - gb_tile_moden = (ARRAY_MODE (ARRAY_2D_TILED_THIN1 ) | -MICRO_TILE_MODE (ADDR_SURF_THIN_MICRO_TILING ) | -PIPE_CONFIG (ADDR_SURF_P4_8x16) | + gb_tile_moden = (MICRO_TILE_MODE (ADDR_SURF_THIN_MICRO_TILING ) | +ARRAY_MODE (ARRAY_2D_TILED_THIN1 ) | +PIPE_CONFIG (ADDR_SURF_P2 ) |TILE_SPLIT (ADDR_SURF_TILE_SPLIT_512B ) | -NUM_BANKS (ADDR_SURF_16_BANK ) |BANK_WIDTH (ADDR_SURF_BANK_WIDTH_1 ) |BANK_HEIGHT (ADDR_SURF_BANK_HEIGHT_1 ) | -MACRO_TILE_ASPECT (ADDR_SURF_MACRO_ASPECT_2 )); +MACRO_TILE_ASPECT (ADDR_SURF_MACRO_ASPECT_2 ) | +NUM_BANKS (ADDR_SURF_16_BANK ));break ;case 17 : - gb_tile_moden = (ARRAY_MODE (ARRAY_2D_TILED_THIN1 ) | -MICRO_TILE_MODE (ADDR_SURF_THIN_MICRO_TILING ) | -PIPE_CONFIG (ADDR_SURF_P4_8x16) | -TILE_SPLIT (split_equal_to_row_size) | + gb_tile_moden = (MICRO_TILE_MODE (ADDR_SURF_THIN_MICRO_TILING ) | +ARRAY_MODE (ARRAY_2D_TILED_THIN1 ) | +PIPE_CONFIG (ADDR_SURF_P2 ) | +BANK_WIDTH (ADDR_SURF_BANK_WIDTH_1 ) | +BANK_HEIGHT (ADDR_SURF_BANK_HEIGHT_1 ) | +MACRO_TILE_ASPECT (ADDR_SURF_MACRO_ASPECT_2 ) |NUM_BANKS (ADDR_SURF_16_BANK ) | +TILE_SPLIT (split_equal_to_row_size)); +break ; +case 18 : + gb_tile_moden = (MICRO_TILE_MODE (ADDR_SURF_THIN_MICRO_TILING ) | +ARRAY_MODE (ARRAY_1D_TILED_THICK ) | +PIPE_CONFIG (ADDR_SURF_P2 )); +break ; +case 19 : + gb_tile_moden = (MICRO_TILE_MODE (ADDR_SURF_THIN_MICRO_TILING ) | +ARRAY_MODE (ARRAY_2D_TILED_XTHICK ) | +PIPE_CONFIG (ADDR_SURF_P2 ) |BANK_WIDTH (ADDR_SURF_BANK_WIDTH_1 ) |BANK_HEIGHT (ADDR_SURF_BANK_HEIGHT_1 ) | -MACRO_TILE_ASPECT (ADDR_SURF_MACRO_ASPECT_2 )); +MACRO_TILE_ASPECT (ADDR_SURF_MACRO_ASPECT_2 ) | +NUM_BANKS (ADDR_SURF_16_BANK ) | +TILE_SPLIT (split_equal_to_row_size)); +break ; +case 20 : + gb_tile_moden = (MICRO_TILE_MODE (ADDR_SURF_THIN_MICRO_TILING ) | +ARRAY_MODE (ARRAY_2D_TILED_THICK ) | +PIPE_CONFIG (ADDR_SURF_P2 ) | +BANK_WIDTH (ADDR_SURF_BANK_WIDTH_1 ) | +BANK_HEIGHT (ADDR_SURF_BANK_HEIGHT_1 ) | +MACRO_TILE_ASPECT (ADDR_SURF_MACRO_ASPECT_2 ) | +NUM_BANKS (ADDR_SURF_16_BANK ) | +TILE_SPLIT (split_equal_to_row_size));break ;case 21 : - gb_tile_moden = (ARRAY_MODE (ARRAY_2D_TILED_THIN1 ) | -MICRO_TILE_MODE (ADDR_SURF_THIN_MICRO_TILING ) | -PIPE_CONFIG (ADDR_SURF_P8_32x32_8x16) | + gb_tile_moden = (MICRO_TILE_MODE (ADDR_SURF_THIN_MICRO_TILING ) | +ARRAY_MODE (ARRAY_2D_TILED_THIN1 ) | +PIPE_CONFIG (ADDR_SURF_P2 ) |TILE_SPLIT (ADDR_SURF_TILE_SPLIT_256B ) | -NUM_BANKS (ADDR_SURF_16_BANK ) |BANK_WIDTH (ADDR_SURF_BANK_WIDTH_2 ) |BANK_HEIGHT (ADDR_SURF_BANK_HEIGHT_4 ) | -MACRO_TILE_ASPECT (ADDR_SURF_MACRO_ASPECT_2 )); +MACRO_TILE_ASPECT (ADDR_SURF_MACRO_ASPECT_1 ) | +NUM_BANKS (ADDR_SURF_8_BANK ));break ;case 22 : - gb_tile_moden = (ARRAY_MODE (ARRAY_2D_TILED_THIN1 ) | -MICRO_TILE_MODE (ADDR_SURF_THIN_MICRO_TILING ) | -PIPE_CONFIG (ADDR_SURF_P8_32x32_8x16) | + gb_tile_moden = (MICRO_TILE_MODE (ADDR_SURF_THIN_MICRO_TILING ) | +ARRAY_MODE (ARRAY_2D_TILED_THIN1 ) | +PIPE_CONFIG (ADDR_SURF_P2 ) |TILE_SPLIT (ADDR_SURF_TILE_SPLIT_256B ) | -NUM_BANKS (ADDR_SURF_16_BANK ) | -BANK_WIDTH (ADDR_SURF_BANK_WIDTH_1 ) | -BANK_HEIGHT (ADDR_SURF_BANK_HEIGHT_4 ) | -MACRO_TILE_ASPECT (ADDR_SURF_MACRO_ASPECT_4 )); +BANK_WIDTH (ADDR_SURF_BANK_WIDTH_2 ) | +BANK_HEIGHT (ADDR_SURF_BANK_HEIGHT_2 ) | +MACRO_TILE_ASPECT (ADDR_SURF_MACRO_ASPECT_1 ) | +NUM_BANKS (ADDR_SURF_8_BANK ));break ;case 23 : - gb_tile_moden = (ARRAY_MODE (ARRAY_2D_TILED_THIN1 ) | -MICRO_TILE_MODE (ADDR_SURF_THIN_MICRO_TILING ) | -PIPE_CONFIG (ADDR_SURF_P8_32x32_8x16) | + gb_tile_moden = (MICRO_TILE_MODE (ADDR_SURF_THIN_MICRO_TILING ) | +ARRAY_MODE (ARRAY_2D_TILED_THIN1 ) | +PIPE_CONFIG (ADDR_SURF_P2 ) |TILE_SPLIT (ADDR_SURF_TILE_SPLIT_256B ) | -NUM_BANKS (ADDR_SURF_16_BANK ) |BANK_WIDTH (ADDR_SURF_BANK_WIDTH_1 ) |BANK_HEIGHT (ADDR_SURF_BANK_HEIGHT_2 ) | -MACRO_TILE_ASPECT (ADDR_SURF_MACRO_ASPECT_2 )); +MACRO_TILE_ASPECT (ADDR_SURF_MACRO_ASPECT_1 ) | +NUM_BANKS (ADDR_SURF_8_BANK ));break ;case 24 : - gb_tile_moden = (ARRAY_MODE (ARRAY_2D_TILED_THIN1 ) | -MICRO_TILE_MODE (ADDR_SURF_THIN_MICRO_TILING ) | -PIPE_CONFIG (ADDR_SURF_P8_32x32_8x16) | + gb_tile_moden = (MICRO_TILE_MODE (ADDR_SURF_THIN_MICRO_TILING ) | +ARRAY_MODE (ARRAY_2D_TILED_THIN1 ) | +PIPE_CONFIG (ADDR_SURF_P2 ) |TILE_SPLIT (ADDR_SURF_TILE_SPLIT_512B ) | -NUM_BANKS (ADDR_SURF_16_BANK ) |BANK_WIDTH (ADDR_SURF_BANK_WIDTH_1 ) |BANK_HEIGHT (ADDR_SURF_BANK_HEIGHT_1 ) | -MACRO_TILE_ASPECT (ADDR_SURF_MACRO_ASPECT_2 )); +MACRO_TILE_ASPECT (ADDR_SURF_MACRO_ASPECT_1 ) | +NUM_BANKS (ADDR_SURF_8_BANK ));break ;case 25 : - gb_tile_moden = (ARRAY_MODE (ARRAY_2D_TILED_THIN1 ) | -MICRO_TILE_MODE (ADDR_SURF_THIN_MICRO_TILING ) | -PIPE_CONFIG (ADDR_SURF_P8_32x32_8x16) | + gb_tile_moden = (MICRO_TILE_MODE (ADDR_SURF_THIN_MICRO_TILING ) | +ARRAY_MODE (ARRAY_2D_TILED_THIN1 ) | +PIPE_CONFIG (ADDR_SURF_P2 ) |TILE_SPLIT (ADDR_SURF_TILE_SPLIT_1KB ) | -NUM_BANKS (ADDR_SURF_8_BANK ) | +BANK_WIDTH (ADDR_SURF_BANK_WIDTH_1 ) | +BANK_HEIGHT (ADDR_SURF_BANK_HEIGHT_2 ) | +MACRO_TILE_ASPECT (ADDR_SURF_MACRO_ASPECT_1 ) | +NUM_BANKS (ADDR_SURF_4_BANK )); +break ; +case 26 : + gb_tile_moden = (MICRO_TILE_MODE (ADDR_SURF_THIN_MICRO_TILING ) | +ARRAY_MODE (ARRAY_2D_TILED_THIN1 ) | +PIPE_CONFIG (ADDR_SURF_P2 ) | +TILE_SPLIT (ADDR_SURF_TILE_SPLIT_1KB ) | +BANK_WIDTH (ADDR_SURF_BANK_WIDTH_1 ) | +BANK_HEIGHT (ADDR_SURF_BANK_HEIGHT_2 ) | +MACRO_TILE_ASPECT (ADDR_SURF_MACRO_ASPECT_1 ) | +NUM_BANKS (ADDR_SURF_4_BANK )); +break ; +case 27 : + gb_tile_moden = (MICRO_TILE_MODE (ADDR_SURF_THIN_MICRO_TILING ) | +ARRAY_MODE (ARRAY_2D_TILED_THIN1 ) | +PIPE_CONFIG (ADDR_SURF_P2 ) | +TILE_SPLIT (ADDR_SURF_TILE_SPLIT_1KB ) | +BANK_WIDTH (ADDR_SURF_BANK_WIDTH_1 ) | +BANK_HEIGHT (ADDR_SURF_BANK_HEIGHT_2 ) | +MACRO_TILE_ASPECT (ADDR_SURF_MACRO_ASPECT_1 ) | +NUM_BANKS (ADDR_SURF_4_BANK )); +break ; +case 28 : + gb_tile_moden = (MICRO_TILE_MODE (ADDR_SURF_THIN_MICRO_TILING ) | +ARRAY_MODE (ARRAY_2D_TILED_THIN1 ) | +PIPE_CONFIG (ADDR_SURF_P2 ) | +TILE_SPLIT (ADDR_SURF_TILE_SPLIT_1KB ) | +BANK_WIDTH (ADDR_SURF_BANK_WIDTH_1 ) | +BANK_HEIGHT (ADDR_SURF_BANK_HEIGHT_2 ) | +MACRO_TILE_ASPECT (ADDR_SURF_MACRO_ASPECT_1 ) | +NUM_BANKS (ADDR_SURF_4_BANK )); +break ; +case 29 : + gb_tile_moden = (MICRO_TILE_MODE (ADDR_SURF_THIN_MICRO_TILING ) | +ARRAY_MODE (ARRAY_2D_TILED_THIN1 ) | +PIPE_CONFIG (ADDR_SURF_P2 ) | +TILE_SPLIT (ADDR_SURF_TILE_SPLIT_1KB ) | +BANK_WIDTH (ADDR_SURF_BANK_WIDTH_1 ) | +BANK_HEIGHT (ADDR_SURF_BANK_HEIGHT_2 ) | +MACRO_TILE_ASPECT (ADDR_SURF_MACRO_ASPECT_1 ) | +NUM_BANKS (ADDR_SURF_4_BANK )); +break ; +case 30 : + gb_tile_moden = (MICRO_TILE_MODE (ADDR_SURF_THIN_MICRO_TILING ) | +ARRAY_MODE (ARRAY_2D_TILED_THIN1 ) | +PIPE_CONFIG (ADDR_SURF_P2 ) | +TILE_SPLIT (ADDR_SURF_TILE_SPLIT_2KB ) |BANK_WIDTH (ADDR_SURF_BANK_WIDTH_1 ) |BANK_HEIGHT (ADDR_SURF_BANK_HEIGHT_1 ) | -MACRO_TILE_ASPECT (ADDR_SURF_MACRO_ASPECT_1 )); +MACRO_TILE_ASPECT (ADDR_SURF_MACRO_ASPECT_1 ) | +NUM_BANKS (ADDR_SURF_4_BANK ));break ;default : - gb_tile_moden =0 ; -break ; +continue ; } adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;WREG32 (mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);