Patch "arm64: KVM: pmu: Reset PMSELR_EL0.SEL to a sane value before entering the guest" has been added to the 4.9-stable tree

This is a note to let you know that I've just added the patch titled

arm64: KVM: pmu: Reset PMSELR_EL0.SEL to a sane value before entering the guest

to the 4.9-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
arm64-kvm-pmu-reset-pmselr_el0.sel-to-a-sane-value-before-entering-the-guest.patch
and it can be found in the queue-4.9 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree, please let <[email protected]> know about it.

From: Marc Zyngier <[email protected]>
Date: Tue, 6 Dec 2016 14:34:22 +0000
Subject: arm64: KVM: pmu: Reset PMSELR_EL0.SEL to a sane value before entering the guest

From: Marc Zyngier <[email protected]>

commit 21cbe3cc8a48ff17059912e019fbde28ed54745a upstream.

The ARMv8 architecture allows the cycle counter to be configured by setting PMSELR_EL0.SEL==0x1f and then accessing PMXEVTYPER_EL0, hence accessing PMCCFILTR_EL0. But it disallows the use of PMSELR_EL0.SEL==0x1f to access the cycle counter itself through PMXEVCNTR_EL0.

Linux itself doesn't violate this rule, but we may end up with PMSELR_EL0.SEL being set to 0x1f when we enter a guest. If that guest accesses PMXEVCNTR_EL0, the access may UNDEF at EL1, despite the guest not having done anything wrong.

In order to avoid this unfortunate course of events (haha!), let's sanitize PMSELR_EL0 on guest entry. This ensures that the guest won't explode unexpectedly.

---
 arch/arm64/kvm/hyp/switch.c |    8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

@@ -85,7 +85,13 @@ static void __hyp_text __activate_traps(
 	write_sysreg(val, hcr_el2);
 	/* Trap on AArch32 cp15 c15 accesses (EL1 or EL0) */
 	write_sysreg(1 << 15, hstr_el2);
-	/* Make sure we trap PMU access from EL0 to EL2 */
+	/*
+	 * Make sure we trap PMU access from EL0 to EL2. Also sanitize
+	 * PMSELR_EL0 to make sure it never contains the cycle
+	 * counter, which could make a PMXEVCNTR_EL0 access UNDEF at
+	 * EL1 instead of being trapped to EL2.
+	 */
+	write_sysreg(0, pmselr_el0);
 	write_sysreg(ARMV8_PMU_USERENR_MASK, pmuserenr_el0);
 	write_sysreg(vcpu->arch.mdcr_el2, mdcr_el2);
 	__activate_traps_arch()();

Patches currently in stable-queue which might be from [email protected] are

queue-4.9/arm64-kvm-pmu-reset-pmselr_el0.sel-to-a-sane-value-before-entering-the-guest.patch