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Patch "drm/i915: Initialize dev_priv->atomic_cdclk_freq at init time" has been added to the 4.8-stable tree

PATCH [email protected] 1 participant 1 message Jan 6, 2017

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This is a note to let you know that I've just added the patch titled

    drm/i915: Initialize dev_priv->atomic_cdclk_freq at init time

to the 4.8-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
drm-i915-initialize-dev_priv-atomic_cdclk_freq-at-init-time.patch
and it can be found in the queue-4.8 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree, please let <[email protected]> know about it.

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From 1f3dc3e334c1192ebe2939ea17ba12f4776f90c3 Mon Sep 17 00:00:00 2001

From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <[email protected]>
Date: Tue, 29 Nov 2016 16:13:57 +0200
Subject: drm/i915: Initialize dev_priv->atomic_cdclk_freq at init time
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Content-Type: text/plain; charset=UTF-8
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From: Ville Syrjälä <[email protected]>

commit 1f3dc3e334c1192ebe2939ea17ba12f4776f90c3 upstream.

Looks like we're only initializing dev_priv->atomic_cdclk_freq at resume and commit times, not at init time. Let's do that as well.

We're now hitting the 'WARN_ON(intel_state->cdclk == 0)' in hsw_compute_linetime_wm() on account of populating intel_state->cdclk from dev_priv->atomic_cdclk_freq. Previously we were mispopulating intel_state->cdclk with dev_priv->cdclk_freq which always had a proper value at init time and hence the WARN_ON() didn't trigger.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=98902

Fixes 14676ec6b1a6 ("drm/i915: Fix cdclk vs. dev_cdclk mess when not recomputing things")
(cherry picked from commit 6a259b1f8a9e99b1ed114f8bf8b0cfccee130e54)
---
 drivers/gpu/drm/i915/intel_display.c |    1 +
 1 file changed, 1 insertion(+)
drivers/gpu/drm/i915/intel_display.c +1 -0
@@ -15904,6 +15904,7 @@ void intel_modeset_init(struct drm_devic
 
 	intel_update_czclk(dev_priv);
 	intel_update_cdclk(dev);
+	dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq;
 
 	intel_shared_dpll_init(dev);
 

Patches currently in stable-queue which might be from [email protected] are

queue-4.8/drm-i915-fix-cdclk-vs.-dev_cdclk-mess-when-not-recomputing-things.patch queue-4.8/drm-i915-dsi-fix-chv_exec_gpio-disabling-the-gpios-it-is-setting.patch queue-4.8/drm-i915-dsi-do-not-clear-dpounit_clock_gate_disable-from-vlv_init_display_clock_gating.patch queue-4.8/drm-i915-initialize-dev_priv-atomic_cdclk_freq-at-init-time.patch