Patch "iommu/vt-d: Fix some macros that are incorrectly specified in intel-iommu" has been added to the 4.10-stable tree
This is a note to let you know that I've just added the patch titled
iommu/vt-d: Fix some macros that are incorrectly specified in intel-iommu
to the 4.10-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
iommu-vt-d-fix-some-macros-that-are-incorrectly-specified-in-intel-iommu.patch
and it can be found in the queue-4.10 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree, please let <[email protected]> know about it.
Quoted 1 line
From
aaa59306b0b7e0ca4ba92cc04c5db101cbb1c096Mon Sep 17 00:00:00 2001
From: CQ Tang <[email protected]>
Date: Mon, 30 Jan 2017 09:39:52 -0800
Subject: iommu/vt-d: Fix some macros that are incorrectly specified in intel-iommu
From: CQ Tang <[email protected]>
commit aaa59306b0b7e0ca4ba92cc04c5db101cbb1c096 upstream.
Some of the macros are incorrect with wrong bit-shifts resulting in picking the incorrect invalidation granularity. Incorrect Source-ID in extended devtlb invalidation caused device side errors.
To: Joerg Roedel <[email protected]>
To: David Woodhouse <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: CQ Tang <[email protected]>
Cc: Ashok Raj <[email protected]>
--- include/linux/intel-iommu.h | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-)
include/linux/intel-iommu.h +7 -7
@@ -153,8 +153,8 @@ static inline void dmar_writeq(void __io#define DMA_TLB_GLOBAL_FLUSH (((u64)1) << 60)#define DMA_TLB_DSI_FLUSH (((u64)2) << 60)#define DMA_TLB_PSI_FLUSH (((u64)3) << 60) -#define DMA_TLB_IIRG (type) ((type >> 60) & 7) -#define DMA_TLB_IAIG (val) (((val) >> 57) & 7) +#define DMA_TLB_IIRG (type) ((type >> 60) & 3) +#define DMA_TLB_IAIG (val) (((val) >> 57) & 3)#define DMA_TLB_READ_DRAIN (((u64)1) << 49)#define DMA_TLB_WRITE_DRAIN (((u64)1) << 48)#define DMA_TLB_DID (id) (((u64)((id) & 0xffff)) << 32)
@@ -164,9 +164,9 @@ static inline void dmar_writeq(void __io/* INVALID_DESC */ #define DMA_CCMD_INVL_GRANU_OFFSET 61 -#define DMA_ID_TLB_GLOBAL_FLUSH (((u64)1) << 3) -#define DMA_ID_TLB_DSI_FLUSH (((u64)2) << 3) -#define DMA_ID_TLB_PSI_FLUSH (((u64)3) << 3) +#define DMA_ID_TLB_GLOBAL_FLUSH (((u64)1) << 4) +#define DMA_ID_TLB_DSI_FLUSH (((u64)2) << 4) +#define DMA_ID_TLB_PSI_FLUSH (((u64)3) << 4)#define DMA_ID_TLB_READ_DRAIN (((u64)1) << 7)#define DMA_ID_TLB_WRITE_DRAIN (((u64)1) << 6)#define DMA_ID_TLB_DID (id) (((u64)((id & 0xffff) << 16)))
@@ -316,8 +316,8 @@ enum {#define QI_DEV_EIOTLB_SIZE (((u64)1) << 11)#define QI_DEV_EIOTLB_GLOB (g) ((u64)g)#define QI_DEV_EIOTLB_PASID (p) (((u64)p) << 32) -#define QI_DEV_EIOTLB_SID (sid) ((u64)((sid) & 0xffff) << 32) -#define QI_DEV_EIOTLB_QDEP (qd) (((qd) & 0x1f) << 16) +#define QI_DEV_EIOTLB_SID (sid) ((u64)((sid) & 0xffff) << 16) +#define QI_DEV_EIOTLB_QDEP (qd) ((u64)((qd) & 0x1f) << 4)#define QI_DEV_EIOTLB_MAX_INVS 32#define QI_PGRP_IDX (idx) (((u64)(idx)) << 55)
Patches currently in stable-queue which might be from [email protected] are
queue-4.10/iommu-vt-d-fix-some-macros-that-are-incorrectly-specified-in-intel-iommu.patch