Patch "MIPS: DEC: Avoid la pseudo-instruction in delay slots" has been added to the 4.4-stable tree
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This is a note to let you know that I've just added the patch titled
MIPS: DEC: Avoid la pseudo-instruction in delay slots
to the 4.4-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
mips-dec-avoid-la-pseudo-instruction-in-delay-slots.patch
and it can be found in the queue-4.4 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree, please let <[email protected]> know about it.
Quoted 1 line
From
3021773c7c3e75e20b693931a19362681e744ea9Mon Sep 17 00:00:00 2001
From: Ralf Baechle <[email protected]>
Date: Tue, 20 Sep 2016 14:33:01 +0200
Subject: MIPS: DEC: Avoid la pseudo-instruction in delay slots
From: Ralf Baechle <[email protected]>
commit 3021773c7c3e75e20b693931a19362681e744ea9 upstream.
When expanding the la or dla pseudo-instruction in a delay slot the GNU assembler will complain should the pseudo-instruction expand to multiple actual instructions, since only the first of them will be in the delay slot leading to the pseudo-instruction being only partially executed if the branch is taken. Use of PTR_LA in the dec int-handler.S leads to such warnings:
arch/mips/dec/int-handler.S: Assembler messages:
arch/mips/dec/int-handler.S:149: Warning: macro instruction expanded into multiple instructions in a branch delay slot arch/mips/dec/int-handler.S:198: Warning: macro instruction expanded into multiple instructions in a branch delay slot
Avoid this by open coding the PTR_LA macros.
--- arch/mips/dec/int-handler.S | 40 ++++++++++++++++++++++++++++++++++++++-- 1 file changed, 38 insertions(+), 2 deletions(-)
arch/mips/dec/int-handler.S +38 -2
@@ -146,7 +146,25 @@ /* * Find irq with highest priority */ - PTR_LA t1,cpu_mask_nr_tbl + # open coded PTR_LA t1, cpu_mask_nr_tbl +#if (_MIPS_SZPTR == 32) + # open coded la t1, cpu_mask_nr_tbl + lui t1, %hi(cpu_mask_nr_tbl) + addiu t1, %lo(cpu_mask_nr_tbl) + +#endif +#if (_MIPS_SZPTR == 64) + # open coded dla t1, cpu_mask_nr_tbl + .set push + .set noat + lui t1, %highest(cpu_mask_nr_tbl) + lui AT, %hi(cpu_mask_nr_tbl) + daddiu t1, t1, %higher(cpu_mask_nr_tbl) + daddiu AT, AT, %lo(cpu_mask_nr_tbl) + dsll t1, 32 + daddu t1, t1, AT + .set pop +#endif 1: lw t2,(t1) nop and t2,t0
@@ -195,7 +213,25 @@ /* * Find irq with highest priority */ - PTR_LA t1,asic_mask_nr_tbl + # open coded PTR_LA t1,asic_mask_nr_tbl +#if (_MIPS_SZPTR == 32) + # open coded la t1, asic_mask_nr_tbl + lui t1, %hi(asic_mask_nr_tbl) + addiu t1, %lo(asic_mask_nr_tbl) + +#endif +#if (_MIPS_SZPTR == 64) + # open coded dla t1, asic_mask_nr_tbl + .set push + .set noat + lui t1, %highest(asic_mask_nr_tbl) + lui AT, %hi(asic_mask_nr_tbl) + daddiu t1, t1, %higher(asic_mask_nr_tbl) + daddiu AT, AT, %lo(asic_mask_nr_tbl) + dsll t1, 32 + daddu t1, t1, AT + .set pop +#endif 2: lw t2,(t1) nop and t2,t0
Patches currently in stable-queue which might be from [email protected] are
queue-4.4/mips-ip27-disable-qlge-driver-in-defconfig.patch queue-4.4/mips-netlogic-fix-cp0_ebase-redefinition-warnings.patch queue-4.4/mips-update-ip27_defconfig-for-scsi_dh-change.patch queue-4.4/mips-dec-avoid-la-pseudo-instruction-in-delay-slots.patch queue-4.4/mips-ralink-cosmetic-change-to-prom_init.patch queue-4.4/mips-ip22-fix-ip28-build-for-modern-gcc.patch queue-4.4/mips-update-lemote2f_defconfig-for-cpu_freq_stat-change.patch queue-4.4/crypto-improve-gcc-optimization-flags-for-serpent-and-wp512.patch queue-4.4/mips-ralink-remove-unused-rt-_wdt_reset-functions.patch queue-4.4/mips-ralink-remove-unused-timer-functions.patch queue-4.4/mips-update-defconfigs-for-nf_ct_proto_dccp-udplite-change.patch