patches for fpga

Hi Greg,

Please take these patches that add FPGA programming via Xilinx slave-serial SPI and Altera PR IP reconfiguration IP. Also some cleanup and adding fpga bindings documentation to the MAINTAINERS file. The one patch by me is needed for the Altera PR IP patchset.

Thanks,
Alan

Alan Tull (1):
fpga: add config complete timeout

Anatolij Gustschin (2):
dt: bindings: fpga: add xilinx slave-serial binding description fpga manager: Add Xilinx slave serial SPI driver

Geert Uytterhoeven (1):
MAINTAINERS: Add file patterns for fpga device tree bindings

Matthew Gerlach (3):
fpga pr ip: Core driver support for Altera Partial Reconfiguration IP. fpga dt: bindings for Altera Partial Reconfiguration IP. fpga pr ip: Platform driver for Altera Partial Reconfiguration IP.

Moritz Fischer (1):
fpga: altera_freeze_bridge: Constify ops

 .../devicetree/bindings/fpga/altera-pr-ip.txt      |  12 ++
 .../bindings/fpga/xilinx-slave-serial.txt          |  44 +++++
 MAINTAINERS                                        |   1 +
 drivers/fpga/Kconfig                               |  19 ++
 drivers/fpga/Makefile                              |   3 +
 drivers/fpga/altera-freeze-bridge.c                |   2 +-
 drivers/fpga/altera-pr-ip-core-plat.c              |  68 +++++++
 drivers/fpga/altera-pr-ip-core.c                   | 220 +++++++++++++++++++++
 drivers/fpga/fpga-region.c                         |   3 +
 drivers/fpga/xilinx-spi.c                          | 198 +++++++++++++++++++
 include/linux/fpga/altera-pr-ip-core.h             |  29 +++
 include/linux/fpga/fpga-mgr.h                      |   3 +
 12 files changed, 601 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/devicetree/bindings/fpga/altera-pr-ip.txt
 create mode 100644 Documentation/devicetree/bindings/fpga/xilinx-slave-serial.txt
 create mode 100644 drivers/fpga/altera-pr-ip-core-plat.c
 create mode 100644 drivers/fpga/altera-pr-ip-core.c
 create mode 100644 drivers/fpga/xilinx-spi.c
 create mode 100644 include/linux/fpga/altera-pr-ip-core.h

2.7.4

From: Moritz Fischer <[email protected]>

The ops are not changing, make them const.

---
 drivers/fpga/altera-freeze-bridge.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

index 8dcd9fb..8c1bc7e 100644
@@ -203,7 +203,7 @@ static int altera_freeze_br_enable_show(struct fpga_bridge *bridge)
 	return priv->enable;
 }
 
-static struct fpga_bridge_ops altera_freeze_br_br_ops = {
+static const struct fpga_bridge_ops altera_freeze_br_br_ops = {
 	.enable_set = altera_freeze_br_enable_set,
 	.enable_show = altera_freeze_br_enable_show,
 };

2.7.4

From: Anatolij Gustschin <[email protected]>

Add dt binding documentation details for Xilinx FPGA configuration over slave serial interface.

---
 .../bindings/fpga/xilinx-slave-serial.txt          | 44 ++++++++++++++++++++++
 1 file changed, 44 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/fpga/xilinx-slave-serial.txt

new file mode 100644
index 0000000..9766f74
@@ -0,0 +1,44 @@
+Xilinx Slave Serial SPI FPGA Manager
+
+Xilinx Spartan-6 FPGAs support a method of loading the bitstream over
+what is referred to as "slave serial" interface.
+The slave serial link is not technically SPI, and might require extra
+circuits in order to play nicely with other SPI slaves on the same bus.
+
+See https://www.xilinx.com/support/documentation/user_guides/ug380.pdf
+
+Required properties:
+- compatible: should contain "xlnx,fpga-slave-serial"
+- reg: spi chip select of the FPGA
+- prog_b-gpios: config pin (referred to as PROGRAM_B in the manual)
+- done-gpios: config status pin (referred to as DONE in the manual)
+
+Example for full FPGA configuration:
+
+	fpga-region0 {
+		compatible = "fpga-region";
+		fpga-mgr = <&fpga_mgr_spi>;
+		#address-cells = <0x1>;
+		#size-cells = <0x1>;
+	};
+
+	spi1: spi@10680 {
+		compatible = "marvell,armada-xp-spi", "marvell,orion-spi";
+		pinctrl-0 = <&spi0_pins>;
+		pinctrl-names = "default";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		cell-index = <1>;
+		interrupts = <92>;
+		clocks = <&coreclk 0>;
+		status = "okay";
+
+		fpga_mgr_spi: fpga-mgr@0 {
+			compatible = "xlnx,fpga-slave-serial";
+			spi-max-frequency = <60000000>;
+			spi-cpha;
+			reg = <0>;
+			done-gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>;
+			prog_b-gpios = <&gpio0 29 GPIO_ACTIVE_LOW>;
+		};
+	};

2.7.4

From: Anatolij Gustschin <[email protected]>

The driver loads FPGA firmware over SPI, using the "slave serial" configuration interface on Xilinx FPGAs.

---
 drivers/fpga/Kconfig      |   7 ++
 drivers/fpga/Makefile     |   1 +
 drivers/fpga/xilinx-spi.c | 198 ++++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 206 insertions(+)
 create mode 100644 drivers/fpga/xilinx-spi.c

index dee470f..c81cb7d 100644
@@ -46,6 +46,13 @@ config FPGA_MGR_TS73XX
 	  FPGA manager driver support for the Altera Cyclone II FPGA
 	  present on the TS-73xx SBC boards.
 
+config FPGA_MGR_XILINX_SPI
+	tristate "Xilinx Configuration over Slave Serial (SPI)"
+	depends on SPI
+	help
+	  FPGA manager driver support for Xilinx FPGA configuration
+	  over slave serial interface.
+
 config FPGA_MGR_ZYNQ_FPGA
 	tristate "Xilinx Zynq FPGA"
 	depends on ARCH_ZYNQ || COMPILE_TEST

index a5ee3ff..c6f5d74 100644
@@ -10,6 +10,7 @@ obj-$(CONFIG_FPGA_MGR_ICE40_SPI)	+= ice40-spi.o
 obj-$(CONFIG_FPGA_MGR_SOCFPGA)		+= socfpga.o
 obj-$(CONFIG_FPGA_MGR_SOCFPGA_A10)	+= socfpga-a10.o
 obj-$(CONFIG_FPGA_MGR_TS73XX)		+= ts73xx-fpga.o
+obj-$(CONFIG_FPGA_MGR_XILINX_SPI)	+= xilinx-spi.o
 obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA)	+= zynq-fpga.o
 
 # FPGA Bridge Drivers

2.7.4

From: Alan Tull <[email protected]>

Adding timeout for maximum allowed time for FPGA to go to operating mode after a FPGA region has been programmed.

---
 drivers/fpga/fpga-region.c    | 3 +++
 include/linux/fpga/fpga-mgr.h | 3 +++
 2 files changed, 6 insertions(+)

index 2fe2a52..ae4c61a 100644
@@ -385,6 +385,9 @@ static int fpga_region_notify_pre_apply(struct fpga_region *region,
 	of_property_read_u32(nd->overlay, "region-freeze-timeout-us",
 			     &info->disable_timeout_us);
 
+	of_property_read_u32(nd->overlay, "config-complete-timeout-us",
+			     &info->config_complete_timeout_us);
+
 	/* If FPGA was externally programmed, don't specify firmware */
 	if ((info->flags & FPGA_MGR_EXTERNAL_CONFIG) && firmware_name) {
 		pr_err("error: specified firmware and external-fpga-config");

index e2ef94f..b4ac24c 100644
@@ -77,11 +77,14 @@ enum fpga_mgr_states {
  * @flags: boolean flags as defined above
  * @enable_timeout_us: maximum time to enable traffic through bridge (uSec)
  * @disable_timeout_us: maximum time to disable traffic through bridge (uSec)
+ * @config_complete_timeout_us: maximum time for FPGA to switch to operating
+ *	   status in the write_complete op.
  */
 struct fpga_image_info {
 	u32 flags;
 	u32 enable_timeout_us;
 	u32 disable_timeout_us;
+	u32 config_complete_timeout_us;
 };
 
 /**

2.7.4

From: Matthew Gerlach <[email protected]>

Adding the core functions necessary for a fpga-mgr driver for the Altera Partial IP component. It is intended for these functions to be used by the various bus implementations like the platform bus or the PCIe bus.

---
 drivers/fpga/Kconfig                   |   5 +
 drivers/fpga/Makefile                  |   1 +
 drivers/fpga/altera-pr-ip-core.c       | 220 +++++++++++++++++++++++++++++++++
 include/linux/fpga/altera-pr-ip-core.h |  29 +++++
 4 files changed, 255 insertions(+)
 create mode 100644 drivers/fpga/altera-pr-ip-core.c
 create mode 100644 include/linux/fpga/altera-pr-ip-core.h

index c81cb7d..e2cc0ad 100644
@@ -83,6 +83,11 @@ config ALTERA_FREEZE_BRIDGE
 	  isolate one region of the FPGA from the busses while that
 	  region is being reprogrammed.
 
+config ALTERA_PR_IP_CORE
+        tristate "Altera Partial Reconfiguration IP Core"
+        help
+          Core driver support for Altera Partial Reconfiguration IP component
+
 endif # FPGA
 
 endmenu

index c6f5d74..968fd51 100644
@@ -12,6 +12,7 @@ obj-$(CONFIG_FPGA_MGR_SOCFPGA_A10)	+= socfpga-a10.o
 obj-$(CONFIG_FPGA_MGR_TS73XX)		+= ts73xx-fpga.o
 obj-$(CONFIG_FPGA_MGR_XILINX_SPI)	+= xilinx-spi.o
 obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA)	+= zynq-fpga.o
+obj-$(CONFIG_ALTERA_PR_IP_CORE)         += altera-pr-ip-core.o
 
 # FPGA Bridge Drivers
 obj-$(CONFIG_FPGA_BRIDGE)		+= fpga-bridge.o

new file mode 100644
index 0000000..3810a90
@@ -0,0 +1,29 @@
+/*
+ * Driver for Altera Partial Reconfiguration IP Core
+ *
+ * Copyright (C) 2016 Intel Corporation
+ *
+ * Based on socfpga-a10.c Copyright (C) 2015-2016 Altera Corporation
+ *  by Alan Tull <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _ALT_PR_IP_CORE_H
+#define _ALT_PR_IP_CORE_H
+#include <linux/io.h>
+
+int alt_pr_register(struct device *dev, void __iomem *reg_base);
+int alt_pr_unregister(struct device *dev);
+
+#endif /* _ALT_PR_IP_CORE_H */

2.7.4

From: Matthew Gerlach <[email protected]>

Device Tree bindings for Altera Partial Reconfiguration IP.

---
 Documentation/devicetree/bindings/fpga/altera-pr-ip.txt | 12 ++++++++++++
 1 file changed, 12 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/fpga/altera-pr-ip.txt

new file mode 100644
index 0000000..52a294c
@@ -0,0 +1,12 @@
+Altera Arria10 Partial Reconfiguration IP
+
+Required properties:
+- compatible : should contain "altr,a10-pr-ip"
+- reg        : base address and size for memory mapped io.
+
+Example:
+
+	fpga_mgr: fpga-mgr@ff20c000 {
+		compatible = "altr,a10-pr-ip";
+		reg = <0xff20c000 0x10>;
+	};

2.7.4

From: Matthew Gerlach <[email protected]>

This adds a platform bus driver for a fpga-mgr driver that uses the Altera Partial Reconfiguration IP component.

---
 drivers/fpga/Kconfig                  |  7 ++++
 drivers/fpga/Makefile                 |  1 +
 drivers/fpga/altera-pr-ip-core-plat.c | 68 +++++++++++++++++++++++++++++++++++
 3 files changed, 76 insertions(+)
 create mode 100644 drivers/fpga/altera-pr-ip-core-plat.c

index e2cc0ad..116ee92 100644
@@ -88,6 +88,13 @@ config ALTERA_PR_IP_CORE
         help
           Core driver support for Altera Partial Reconfiguration IP component
 
+config ALTERA_PR_IP_CORE_PLAT
+	tristate "Platform support of Altera Partial Reconfiguration IP Core"
+	depends on ALTERA_PR_IP_CORE && OF && HAS_IOMEM
+	help
+	  Platform driver support for Altera Partial Reconfiguration IP
+	  component
+
 endif # FPGA
 
 endmenu

index 968fd51..530cf94 100644
@@ -13,6 +13,7 @@ obj-$(CONFIG_FPGA_MGR_TS73XX)		+= ts73xx-fpga.o
 obj-$(CONFIG_FPGA_MGR_XILINX_SPI)	+= xilinx-spi.o
 obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA)	+= zynq-fpga.o
 obj-$(CONFIG_ALTERA_PR_IP_CORE)         += altera-pr-ip-core.o
+obj-$(CONFIG_ALTERA_PR_IP_CORE_PLAT)    += altera-pr-ip-core-plat.o
 
 # FPGA Bridge Drivers
 obj-$(CONFIG_FPGA_BRIDGE)		+= fpga-bridge.o

2.7.4

From: Geert Uytterhoeven <[email protected]>

Submitters of device tree binding documentation may forget to CC the subsystem maintainer if this is missing.

---
 MAINTAINERS | 1 +
 1 file changed, 1 insertion(+)

index c8f88d0..88e893d 100644
@@ -5189,6 +5189,7 @@ R:	Moritz Fischer <[email protected]>
 L:	[email protected]
 S:	Maintained
 T:	git git://git.kernel.org/pub/scm/linux/kernel/git/atull/linux-fpga.git
+F:	Documentation/devicetree/bindings/fpga/
 F:	drivers/fpga/
 F:	include/linux/fpga/fpga-mgr.h
 W:	http://www.rocketboards.org

2.7.4