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Device Tree Binding for Intel FPGA Video and Image Processing Suite

PATCH Ong, Hean Loong 2 participants 6 messages Mar 31, 2017 – Apr 8, 2017 5 messages not in the archive

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Ong, Hean Loong

author
#0 lore raw

Hi Rob,

I would like to upstream the attached device tree binding patch to the community. This is required for the support of framebuffer drivers of the Intel FPGA Video and Image Processing Suite intended for the Arria10 devkit.

The device tree information includes the maximum width and height supported by the framebuffer display. These are fixed parameters determined by the use who the Quartus design system to program the FPGA in the Arria10 devkit and its variants.

BR

Hean Loong

From 23a9e274bb517b8e232c5aa4cf9737de1644b708 Mon Sep 17 00:00:00 2001
From: Ong, Hean Loong <[email protected]>
Date: Thu, 30 Mar 2017 17:59:37 +0800
Subject: [PATCHv0] Intel FPGA Video and Image Processing Suite device tree binding

Device tree binding for Intel FPGA Video and Image Processing Suite. The binding involved would be generated from the Altera (Intel) Qsys system. The bindings would set the max width, max height, buts per pixel and memory port width. The device tree binding only supports the Intel Arria10 devkit and its variants. Vendor name retained as altr.

Signed-off-by Ong, Hean Loong <[email protected]>
---
 .../devicetree/bindings/gpu/altr,vip-fb2.txt       |   24 ++++++++++++++++++++
 1 files changed, 24 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/gpu/altr,vip-fb2.txt
Documentation/devicetree/bindings/gpu/altr,vip-fb2.txt new file +24 -0
new file mode 100644
index 0000000..9ba3209
@@ -0,0 +1,24 @@
+Intel Video and Image Processing(VIP) Frame Buffer II bindings
+
+Supported hardware:  Arria 10 and above with display port IP
+
+Required properties:
+- compatible: "altr,vip-frame-buffer-2.0"
+- reg: Physical base address and length of the framebuffer controller's
+  registers.
+- max-width: The width of the framebuffer in pixels.
+- max-height: The height of the framebuffer in pixels.
+- bits-per-symbol: only "8" is currently supported
+- mem-port-width = the bus width of the avalon master port on the frame reader
+
+Example:
+
+dp_0_frame_buf: vip@0x100000280 {
+	compatible = "altr,vip-frame-buffer-2.0";
+	reg = <0x00000001 0x00000280 0x00000040>;
+	altr,max-width = <1280>;
+	altr,max-height = <720>;
+	altr,bits-per-symbol = <8>;
+	altr,mem-port-width = <128>;
+};
+
Signature · 1 line
1.7.1
#2 lore raw
In reply to a message not in the archive
Quoted 11 lines · Hean Loong

Hi Rob,

I would like to upstream the attached device tree binding patch to the community. This is required for the support of framebuffer drivers of the Intel FPGA Video and Image Processing Suite intended for the Arria10 devkit.

The device tree information includes the maximum width and height supported by the framebuffer display. These are fixed parameters determined by the use who the Quartus design system to program the FPGA in the Arria10 devkit and its variants.

Please read Documentation/devicetree/bindings/submitting-patches.txt.

The first problem is sending the patch as an attachment.

Rob
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author
#4 lore raw
In reply to a message not in the archive

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author
#6 lore raw
In reply to a message not in the archive

Hi Rob,

Any comments on the patch?

BR

Hean Loong

Quoted 60 lines · Hean Loong

Hi Rob,

Apologies for the mistake. Below are the bindings

From 23a9e274bb517b8e232c5aa4cf9737de1644b708 Mon Sep 17 00:00:00 2001
From: Ong, Hean Loong <[email protected]>
Date: Thu, 30 Mar 2017 17:59:37 +0800
Subject: [PATCHv0] Intel FPGA Video and Image Processing Suite device tree binding

        Device tree binding for Intel FPGA Video and Image Processing Suite. The binding involved would be generated from the Altera (Intel) Qsys system. The bindings would set the max width, max height, buts per pixel and memory port width. The device tree binding only supports the Intel Arria10 devkit and its variants. Vendor name retained as altr.

Signed-off-by Ong, Hean Loong <[email protected]>

---
 .../devicetree/bindings/gpu/altr,vip-fb2.txt       |   24
++++++++++++++++++++

 1 files changed, 24 insertions(+), 0 deletions(-)

 create mode 100644 Documentation/devicetree/bindings/gpu/altr,vip- fb2.txt

Documentation/devicetree/bindings/gpu/altr,vip-fb2.txt new file +7 -0
new file mode 100644
index 0000000..9ba3209
@@ -0,0 +1,24 @@
+Intel Video and Image Processing(VIP) Frame Buffer II bindings
+
+Supported hardware:  Arria 10 and above with display port IP
+
+Required properties:
+- compatible: "altr,vip-frame-buffer-2.0"
+- reg: Physical base address and length of the framebuffer

controller's
+  registers.

+- max-width: The width of the framebuffer in pixels.
+- max-height: The height of the framebuffer in pixels.
+- bits-per-symbol: only "8" is currently supported
+- mem-port-width = the bus width of the avalon master port on the

frame reader

Documentation/devicetree/bindings/gpu/altr,vip-fb2.txt new file +12 -0
+
+Example:
+
+dp_0_frame_buf: vip@0x100000280 {
+       compatible = "altr,vip-frame-buffer-2.0";
+       reg = <0x00000001 0x00000280 0x00000040>;
+       altr,max-width = <1280>;
+       altr,max-height = <720>;
+       altr,bits-per-symbol = <8>;
+       altr,mem-port-width = <128>;
+};
+
Quoted 3 lines

--
1.7.1

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#8 lore raw
In reply to a message not in the archive
Quoted 3 lines · Hean Loong

Hi Rob,

Any comments on the patch?

Yes, the same ones I provided 5 months ago to you. Repeated below.

Quoted 16 lines

BR

Hean Loong

Quoted 10 lines · Hean Loong

Hi Rob,

Apologies for the mistake. Below are the bindings

From 23a9e274bb517b8e232c5aa4cf9737de1644b708 Mon Sep 17 00:00:00 2001
From: Ong, Hean Loong <[email protected]>
Date: Thu, 30 Mar 2017 17:59:37 +0800
Subject: [PATCHv0] Intel FPGA Video and Image Processing Suite device tree binding

This is still not how you email patches. The easiest way is git-send-email.

Quoted 7 lines
Quoted 7 lines

Device tree binding for Intel FPGA Video and Image Processing Suite. The binding involved would be generated from the Altera (Intel) Qsys system. The bindings would set the max width, max height, buts per pixel and memory port width. The device tree binding only supports the Intel Arria10 devkit and its variants. Vendor name retained as altr.

There should be no indentation here.

Quoted 5 lines
Quoted 5 lines
Signed-off-by Ong, Hean Loong <[email protected]>
---
 .../devicetree/bindings/gpu/altr,vip-fb2.txt       |   24

++++++++++++++++++++

bindings/display/. This is not a GPU.

Quoted 21 lines
Quoted 20 lines
 1 files changed, 24 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/gpu/altr,vip-

fb2.txt

Documentation/devicetree/bindings/gpu/altr,vip-fb2.txt new file +7 -0
new file mode 100644
index 0000000..9ba3209
@@ -0,0 +1,24 @@
+Intel Video and Image Processing(VIP) Frame Buffer II bindings
+
+Supported hardware:  Arria 10 and above with display port IP
+
+Required properties:
+- compatible: "altr,vip-frame-buffer-2.0"
+- reg: Physical base address and length of the framebuffer

controller's
+ registers.

Quoted 3 lines
Quoted 3 lines
+- max-width: The width of the framebuffer in pixels.
+- max-height: The height of the framebuffer in pixels.
+- bits-per-symbol: only "8" is currently supported

Why do these need to be in DT?

Quoted 2 lines
Quoted 2 lines

+- mem-port-width = the bus width of the avalon master port on the frame reader

Still needs a vendor prefix.

Quoted 4 lines

Documentation/devicetree/bindings/gpu/altr,vip-fb2.txt

Quoted 4 lines
Documentation/devicetree/bindings/gpu/altr,vip-fb2.txt new file +4 -0
+
+Example:
+
+dp_0_frame_buf: vip@0x100000280 {

display-controller@100000280

Quoted 11 lines
Quoted 11 lines
Documentation/devicetree/bindings/gpu/altr,vip-fb2.txt new file +8 -1
+       compatible = "altr,vip-frame-buffer-2.0";
+       reg = <0x00000001 0x00000280 0x00000040>;
+       altr,max-width = <1280>;
+       altr,max-height = <720>;
+       altr,bits-per-symbol = <8>;
+       altr,mem-port-width = <128>;
+};
+
--

1.7.1

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author
#10 lore raw
In reply to a message not in the archive

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