Device Tree Binding for Intel FPGA Video and Image Processing Suite

Hi Rob,

I am resubmitting the patch again since the last doesn't comply with the rules of the community.

From: Ong, Hean Loong <[email protected]>
Date: Thu, 30 Mar 2017 17:59:37 +0800
Subject: [PATCHv0] Intel FPGA Video and Image Processing Suite device tree binding

        Device tree binding for Intel FPGA Video and Image Processing Suite. The binding involved would be generated from the Altera (Intel) Qsys system. The bindings would set the max width, max height, buts per pixel and memory port width. The device tree binding only supports the Intel Arria10 devkit and its variants. Vendor name retained as altr.

---
 .../devicetree/bindings/gpu/altr,vip-fb2.txt       |   24
++++++++++++++++++++

 1 files changed, 24 insertions(+), 0 deletions(-)

 create mode 100644 Documentation/devicetree/bindings/gpu/altr,vip- fb2.txt

b/Documentation/devicetree/bindings/gpu/altr,vip-fb2.txt new file mode 100644
index 0000000..9ba3209

@@ -0,0 +1,24 @@
+Intel Video and Image Processing(VIP) Frame Buffer II bindings
+
+Supported hardware:  Arria 10 and above with display port IP
+
+Required properties:
+- compatible: "altr,vip-frame-buffer-2.0"
+- reg: Physical base address and length of the framebuffer

controller's
+  registers.

+- max-width: The width of the framebuffer in pixels.
+- max-height: The height of the framebuffer in pixels.
+- bits-per-symbol: only "8" is currently supported
+- mem-port-width = the bus width of the avalon master port on the

frame reader
+
+Example:
+
+dp_0_frame_buf: vip@0x100000280 {
+       compatible = "altr,vip-frame-buffer-2.0";
+       reg = <0x00000001 0x00000280 0x00000040>;
+       altr,max-width = <1280>;
+       altr,max-height = <720>;
+       altr,bits-per-symbol = <8>;
+       altr,mem-port-width = <128>;
+};
+
--
1.7.1

BR

Hean-Loong
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