Patch "MIPS: Add MIPS_CPU_FTLB for Loongson-3A R2" has been added to the 4.9-stable tree

This is a note to let you know that I've just added the patch titled

MIPS: Add MIPS_CPU_FTLB for Loongson-3A R2

to the 4.9-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
mips-add-mips_cpu_ftlb-for-loongson-3a-r2.patch
and it can be found in the queue-4.9 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree, please let <[email protected]> know about it.

From: Huacai Chen <[email protected]>
Date: Thu, 16 Mar 2017 21:00:25 +0800
Subject: MIPS: Add MIPS_CPU_FTLB for Loongson-3A R2

From: Huacai Chen <[email protected]>

commit 033cffeedbd11c140952b98e8639bf652091a17d upstream.

Loongson-3A R2 and newer CPU have FTLB, but Config0.MT is 1, so add MIPS_CPU_FTLB to the CPU options.

Patchwork: https://patchwork.linux-mips.org/patch/15752/

---
 arch/mips/kernel/cpu-probe.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

@@ -1824,7 +1824,7 @@ static inline void cpu_probe_loongson(st
 		}
 
 		decode_configs(c);
-		c->options |= MIPS_CPU_TLBINV | MIPS_CPU_LDPTE;
+		c->options |= MIPS_CPU_FTLB | MIPS_CPU_TLBINV | MIPS_CPU_LDPTE;
 		c->writecombine = _CACHE_UNCACHED_ACCELERATED;
 		break;
 	default:

Patches currently in stable-queue which might be from [email protected] are

queue-4.9/mips-flush-wrong-invalid-ftlb-entry-for-huge-page.patch queue-4.9/mips-check-tlb-before-handle_ri_rdhwr-for-loongson-3.patch queue-4.9/mips-c-r4k-fix-loongson-3-s-vcache-scache-waysize-calculation.patch queue-4.9/mips-add-mips_cpu_ftlb-for-loongson-3a-r2.patch