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arm: socfpga: add cyclone5 based de10-nano board

PATCH New Dalon Westergreen 3 participants 6 messages Apr 18, 2017 – Apr 19, 2017

Subsystems (3)
Arm (32-bit) Arm sub-architectures Arm/socfpga architecture
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Dalon Westergreen

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#0 lore raw

PATCH 1/1 arm: socfpga: add cyclone5 based de10-nano board

Add support for the Terasic DE10-Nano board. The board is based on the DE0-Nano-Soc board but adds a larger FPGA and an HDMI output.

Signed-off-by Dalon Westergreen <[email protected]>
---
 arch/arm/dts/Makefile                       |   1 +
 arch/arm/dts/socfpga_cyclone5_de10_nano.dts |  68 +++
 arch/arm/mach-socfpga/Kconfig               |   7 +
 board/terasic/de10-nano/MAINTAINERS         |   5 +
 board/terasic/de10-nano/Makefile            |   9 +
 board/terasic/de10-nano/qts/iocsr_config.h  | 660 ++++++++++++++++++++++++++++
 board/terasic/de10-nano/qts/pinmux_config.h | 219 +++++++++
 board/terasic/de10-nano/qts/pll_config.h    |  85 ++++
 board/terasic/de10-nano/qts/sdram_config.h  | 344 +++++++++++++++
 board/terasic/de10-nano/socfpga.c           |   6 +
 configs/socfpga_de10_nano_defconfig         |  59 +++
 include/configs/socfpga_de10_nano.h         |  33 ++
 12 files changed, 1496 insertions(+)
 create mode 100644 arch/arm/dts/socfpga_cyclone5_de10_nano.dts
 create mode 100644 board/terasic/de10-nano/MAINTAINERS
 create mode 100644 board/terasic/de10-nano/Makefile
 create mode 100644 board/terasic/de10-nano/qts/iocsr_config.h
 create mode 100644 board/terasic/de10-nano/qts/pinmux_config.h
 create mode 100644 board/terasic/de10-nano/qts/pll_config.h
 create mode 100644 board/terasic/de10-nano/qts/sdram_config.h
 create mode 100644 board/terasic/de10-nano/socfpga.c
 create mode 100644 configs/socfpga_de10_nano_defconfig
 create mode 100644 include/configs/socfpga_de10_nano.h
arch/arm/dts/Makefile +1 -0
index ce34e3e..699cbd6 100644
@@ -153,6 +153,7 @@ dtb-$(CONFIG_ARCH_SOCFPGA) +=				\
 	socfpga_cyclone5_socdk.dtb			\
 	socfpga_cyclone5_de0_nano_soc.dtb			\
 	socfpga_cyclone5_de1_soc.dtb			\
+	socfpga_cyclone5_de10_nano.dtb			\
 	socfpga_cyclone5_sockit.dtb			\
 	socfpga_cyclone5_socrates.dtb			\
 	socfpga_cyclone5_sr1500.dtb			\
arch/arm/dts/socfpga_cyclone5_de10_nano.dts new file +68 -0

68 lines not on this page · raw message

arch/arm/mach-socfpga/Kconfig +7 -0
index 9bfee04..f6e5773 100644
@@ -82,6 +82,10 @@ config TARGET_SOCFPGA_TERASIC_DE0_NANO
 	bool "Terasic DE0-Nano-Atlas (Cyclone V)"
 	select TARGET_SOCFPGA_CYCLONE5
 
+config TARGET_SOCFPGA_TERASIC_DE10_NANO
+	bool "Terasic DE10-Nano (Cyclone V)"
+	select TARGET_SOCFPGA_CYCLONE5
+
 config TARGET_SOCFPGA_TERASIC_DE1_SOC
 	bool "Terasic DE1-SoC (Cyclone V)"
 	select TARGET_SOCFPGA_CYCLONE5

@@ -97,6 +101,7 @@ config SYS_BOARD
 	default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
 	default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
 	default "de1-soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
+	default "de10-nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
 	default "is1" if TARGET_SOCFPGA_IS1
 	default "mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK
 	default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT

@@ -112,6 +117,7 @@ config SYS_VENDOR
 	default "samtec" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
 	default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
 	default "terasic" if TARGET_SOCFPGA_TERASIC_DE1_SOC
+	default "terasic" if TARGET_SOCFPGA_TERASIC_DE10_NANO
 	default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT
 
 config SYS_SOC

@@ -122,6 +128,7 @@ config SYS_CONFIG_NAME
 	default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
 	default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
 	default "socfpga_de1_soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
+	default "socfpga_de10_nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
 	default "socfpga_is1" if TARGET_SOCFPGA_IS1
 	default "socfpga_mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK
 	default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
board/terasic/de10-nano/MAINTAINERS new file +5 -0
new file mode 100644
index 0000000..f4dd0df
@@ -0,0 +1,5 @@
+DE10-NANO BOARD
+M:	Dalon Westergreen <[email protected]>
+S:	Maintained
+F:	include/configs/socfpga_de10_nano.h
+F:	configs/socfpga_de10_nano_defconfig
board/terasic/de10-nano/Makefile new file +9 -0
new file mode 100644
index 0000000..ab38f42
@@ -0,0 +1,9 @@
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+# Copyright (C) 2017, Intel Corporation
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	:= socfpga.o
board/terasic/de10-nano/qts/iocsr_config.h new file +660 -0

660 lines not on this page · raw message

board/terasic/de10-nano/qts/pinmux_config.h new file +219 -0

219 lines not on this page · raw message

board/terasic/de10-nano/qts/pll_config.h new file +85 -0

85 lines not on this page · raw message

board/terasic/de10-nano/qts/sdram_config.h new file +344 -0

344 lines not on this page · raw message

board/terasic/de10-nano/socfpga.c new file +6 -0
new file mode 100644
index 0000000..c5852e7
@@ -0,0 +1,6 @@
+/*
+ * Copyright (C) 2017, Intel Corporation
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#include <common.h>
configs/socfpga_de10_nano_defconfig new file +59 -0

59 lines not on this page · raw message

include/configs/socfpga_de10_nano.h new file +33 -0
new file mode 100644
index 0000000..302ec20
@@ -0,0 +1,33 @@
+/*
+ * Copyright (C) 2017, Intel Corporation
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef __CONFIG_TERASIC_DE10_H__
+#define __CONFIG_TERASIC_DE10_H__
+
+#include <asm/arch/base_addr_ac5.h>
+
+/* U-Boot Commands */
+#define CONFIG_FAT_WRITE
+#define CONFIG_HW_WATCHDOG
+
+/* Memory configurations */
+#define PHYS_SDRAM_1_SIZE		0x40000000	/* 1GiB */
+
+/* Booting Linux */
+#define CONFIG_LOADADDR		0x01000000
+#define CONFIG_SYS_LOAD_ADDR	CONFIG_LOADADDR
+
+/* Ethernet on SoC (EMAC) */
+#if defined(CONFIG_CMD_NET)
+#define CONFIG_PHY_MICREL
+#define CONFIG_PHY_MICREL_KSZ9031
+#endif
+
+#define CONFIG_ENV_IS_IN_MMC
+
+/* The rest of the configuration is shared */
+#include <configs/socfpga_common.h>
+
+#endif	/* __CONFIG_TERASIC_DE10_H__ */
Signature · 1 line
2.7.4
#1 lore raw

PATCH 1/1 arm: socfpga: add cyclone5 based de10-nano board

Quoted 5 lines · Dalon Westergreen

Add support for the Terasic DE10-Nano board. The board is based on the DE0-Nano-Soc board but adds a larger FPGA and an HDMI output.

Signed-off-by Dalon Westergreen <[email protected]>

[...]

board/terasic/de10-nano/Makefile line 6

Quoted 12 lines
board/terasic/de10-nano/Makefile new file +6 -0
new file mode 100644
index 0000000..ab38f42
@@ -0,0 +1,9 @@
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+# Copyright (C) 2017, Intel Corporation
+#
+# SPDX-License-Identifier:	GPL-2.0+

The SPDX identifier is here twice (at least it's twice the same :)), drop one.

board/terasic/de10-nano/Makefile line 9

Quoted 2 lines
board/terasic/de10-nano/Makefile new file +2 -0
+
+obj-y	:= socfpga.o

Wasn't this patch submitted to the ML already once ? Anyway, looks OK expect for the nit.

Signature · 2 lines
Best regards,
Marek Vasut
author
#2 lore raw

PATCH 1/1 arm: socfpga: add cyclone5 based de10-nano board

Quoted 29 lines · Marek Vasut
Quoted 6 lines · Dalon Westergreen

Add support for the Terasic DE10-Nano board.  The board is based on the DE0-Nano-Soc board but adds a larger FPGA and an HDMI output.

Signed-off-by Dalon Westergreen <[email protected]>

[...]

Quoted 8 lines
board/terasic/de10- renamed from board/terasic/de10-nano/Makefile +0 -0

nano/Makefile
new file mode 100644
index 0000000..ab38f42

board/terasic/de10-nano/Makefile line 6

Quoted 6 lines
board/terasic/de10-nano/Makefile new file +6 -0
@@ -0,0 +1,9 @@
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+# Copyright (C) 2017, Intel Corporation
+#
+# SPDX-License-Identifier:	GPL-2.0+

The SPDX identifier is here twice (at least it's twice the same :)), drop one.

Quoted 1 line
Quoted 6 lines

board/terasic/de10-nano/Makefile line 9

Quoted 2 lines
board/terasic/de10-nano/Makefile new file +2 -0
+
+obj-y	:= socfpga.o

Wasn't this patch submitted to the ML already once ? Anyway, looks OK expect for the nit.

I believe it was dropped from a patch set including a bunch of boards with the suggestion it should be a separate patch.  I am just getting back to it.

--dalon

#3 lore raw

PATCH 1/1 arm: socfpga: add cyclone5 based de10-nano board

Quoted 30 lines · Dalon Westergreen
Quoted 29 lines · Marek Vasut
Quoted 6 lines · Dalon Westergreen

Add support for the Terasic DE10-Nano board. The board is based on the DE0-Nano-Soc board but adds a larger FPGA and an HDMI output.

Signed-off-by Dalon Westergreen <[email protected]>

[...]

Quoted 8 lines
board/terasic/de10- renamed from board/terasic/de10-nano/Makefile +0 -0

nano/Makefile
new file mode 100644
index 0000000..ab38f42

board/terasic/de10-nano/Makefile line 6

Quoted 6 lines
board/terasic/de10-nano/Makefile new file +6 -0
@@ -0,0 +1,9 @@
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+# Copyright (C) 2017, Intel Corporation
+#
+# SPDX-License-Identifier:	GPL-2.0+

The SPDX identifier is here twice (at least it's twice the same :)), drop one.

Quoted 1 line
Quoted 8 lines
Quoted 6 lines

board/terasic/de10-nano/Makefile line 9

Quoted 2 lines
board/terasic/de10-nano/Makefile new file +2 -0
+
+obj-y	:= socfpga.o

Wasn't this patch submitted to the ML already once ? Anyway, looks OK expect for the nit.

I believe it was dropped from a patch set including a bunch of boards with the suggestion it should be a separate patch. I am just getting back to it.

Ah ok, super, then fix this detail, get an A-B/R-B from Dinh and I'll pick it.

Signature · 2 lines
Best regards,
Marek Vasut
#4 lore raw

PATCH 1/1 arm: socfpga: add cyclone5 based de10-nano board

Quoted 37 lines · Marek Vasut
Quoted 36 lines · Dalon Westergreen
Quoted 35 lines · Marek Vasut
Quoted 6 lines · Dalon Westergreen

Add support for the Terasic DE10-Nano board. The board is based on the DE0-Nano-Soc board but adds a larger FPGA and an HDMI output.

Signed-off-by Dalon Westergreen <[email protected]>

[...]

Quoted 8 lines
board/terasic/de10- renamed from board/terasic/de10-nano/Makefile +0 -0

nano/Makefile
new file mode 100644
index 0000000..ab38f42

board/terasic/de10-nano/Makefile line 6

Quoted 6 lines
board/terasic/de10-nano/Makefile new file +6 -0
@@ -0,0 +1,9 @@
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2017, Intel Corporation
+#
+# SPDX-License-Identifier: GPL-2.0+

The SPDX identifier is here twice (at least it's twice the same :)), drop one.

board/terasic/de10-nano/Makefile line 9

Quoted 3 lines
board/terasic/de10-nano/Makefile new file +2 -0
+
+obj-y      := socfpga.o

Wasn't this patch submitted to the ML already once ? Anyway, looks OK expect for the nit.

Quoted 6 lines
Quoted 2 lines

I believe it was dropped from a patch set including a bunch of boards with the suggestion it should be a separate patch. I am just getting back to it.

Ah ok, super, then fix this detail, get an A-B/R-B from Dinh and I'll pick it.

Reviewed-by Dinh Nguyen <[email protected]>
Applied
#5 lore raw

PATCH 1/1 arm: socfpga: add cyclone5 based de10-nano board

Quoted 38 lines · Dinh Nguyen
Quoted 37 lines · Marek Vasut
Quoted 36 lines · Dalon Westergreen
Quoted 35 lines · Marek Vasut
Quoted 6 lines · Dalon Westergreen

Add support for the Terasic DE10-Nano board. The board is based on the DE0-Nano-Soc board but adds a larger FPGA and an HDMI output.

Signed-off-by Dalon Westergreen <[email protected]>

[...]

Quoted 8 lines
board/terasic/de10- renamed from board/terasic/de10-nano/Makefile +0 -0

nano/Makefile
new file mode 100644
index 0000000..ab38f42

board/terasic/de10-nano/Makefile line 6

Quoted 6 lines
board/terasic/de10-nano/Makefile new file +6 -0
@@ -0,0 +1,9 @@
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2017, Intel Corporation
+#
+# SPDX-License-Identifier: GPL-2.0+

The SPDX identifier is here twice (at least it's twice the same :)), drop one.

board/terasic/de10-nano/Makefile line 9

Quoted 3 lines
board/terasic/de10-nano/Makefile new file +2 -0
+
+obj-y      := socfpga.o

Wasn't this patch submitted to the ML already once ? Anyway, looks OK expect for the nit.

Quoted 9 lines
Quoted 6 lines
Quoted 2 lines

I believe it was dropped from a patch set including a bunch of boards with the suggestion it should be a separate patch. I am just getting back to it.

Ah ok, super, then fix this detail, get an A-B/R-B from Dinh and I'll pick it.

Reviewed-by Dinh Nguyen <[email protected]>

Applied to socfpga/next, thanks !

Signature · 2 lines
Best regards,
Marek Vasut